SAK-XC2267-96F66L AC Infineon Technologies, SAK-XC2267-96F66L AC Datasheet - Page 94
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SAK-XC2267-96F66L AC
Manufacturer Part Number
SAK-XC2267-96F66L AC
Description
IC MCU 16BIT FLASH PG-LQFP-100
Manufacturer
Infineon Technologies
Series
XC22xxr
Datasheet
1.SAK-XC2264-56F66L_AC.pdf
(116 pages)
Specifications of SAK-XC2267-96F66L AC
Core Processor
C166SV2
Core Size
16/32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, I²C, LIN, SPI, SSC, UART/USART, USI
Peripherals
DMA, I²S, POR, PWM, WDT
Number Of I /o
75
Program Memory Size
768KB (768K x 8)
Program Memory Type
FLASH
Ram Size
82K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
100-LFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
KX226796F66L82ACXT
SAK-XC2267-96F66L82 AC
SAK-XC2267-96F66L82ACINTR
SAK-XC2267-96F66L82ACINTR
SAK-XC2267-96F66LACINTR
SP000250942
SAK-XC2267-96F66L82 AC
SAK-XC2267-96F66L82ACINTR
SAK-XC2267-96F66L82ACINTR
SAK-XC2267-96F66LACINTR
SP000250942
Direct Drive
When direct drive operation is selected (SYSCON0.CLKSEL = 11
derived directly from the input clock signal CLKIN1:
f
The frequency of
times of
Selecting Bypass Operation from the XTAL1
in a similar configuration.
Prescaler Operation
When prescaler operation is selected (SYSCON0.CLKSEL = 10
1
XTAL1) or from the internal clock source through the output prescaler K1 (= K1DIV+1):
f
If a divider factor of 1 is selected, the frequency of
this case the high and low times of
clock
The lowest system clock frequency results from selecting the maximum value for the
divider factor K1:
f
Phase Locked Loop (PLL)
When PLL operation is selected (SYSCON0.CLKSEL = 10
the on-chip phase locked loop is enabled and provides the system clock. The PLL
multiplies the input frequency by the factor F (
F is calculated from the input divider P (= PDIV+1), the multiplication factor N (=
NDIV+1), and the output divider K2 (= K2DIV+1):
(F = N / (P × K2)).
The input clock can be derived either from an external source at XTAL1 or from the on-
chip clock source.
The PLL circuit synchronizes the system clock to the input clock. This synchronization is
performed smoothly so that the system clock frequency does not change abruptly.
Adjustment to the input clock continuously changes the frequency of
locked to
of individual TCSs.
1) Voltages on XTAL1 must comply to the core supply voltage
Data Sheet
SYS
SYS
SYS
B
), the system clock is derived either from the crystal oscillator (input clock signal
=
=
=
f
f
f
f
OSC
IN
OSC
OSC
f
.
SYS
f
(external or internal).
IN
/ K1.
/ 1024.
. The slight variation causes a jitter of
are determined by the duty cycle of the input clock
f
SYS
is the same as the frequency of
f
SYS
are determined by the duty cycle of the input
92
1)
input and using a divider factor of 1 results
f
SYS
V
f
=
DDI1
SYS
f
SYS
f
IN
.
which in turn affects the duration
f
× F).
XC2000 Family Derivatives
IN
equals the frequency of
. In this case the high and low
B
, PLLCON0.VCOBY = 0
f
B
Electrical Parameters
IN
, PLLCON0.VCOBY =
B
.
), the system clock is
XC2267 / XC2264
f
SYS
V2.1, 2008-08
so that it is
f
OSC
. In
B
),