SAK-C161CS-LF CA Infineon Technologies, SAK-C161CS-LF CA Datasheet - Page 14
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SAK-C161CS-LF CA
Manufacturer Part Number
SAK-C161CS-LF CA
Description
IC MCU 16BIT 256KB TQFP-128-2
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet
1.SAK-C161CS-LF_CA.pdf
(89 pages)
Specifications of SAK-C161CS-LF CA
Core Processor
C166
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
93
Program Memory Type
ROMless
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
128-LFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Other names
K161CSLFCANP
K161CSLFCAXT
SAK-C161CS-LFCA
SAK-C161CS-LFCAINTR
SAK-C161CS-LFCATR
SAK-C161CS-LFCATR
SAKC161CSLFCAXT
SP000106869
K161CSLFCAXT
SAK-C161CS-LFCA
SAK-C161CS-LFCAINTR
SAK-C161CS-LFCATR
SAK-C161CS-LFCATR
SAKC161CSLFCAXT
SP000106869
Table 2
Symbol Pin
P4
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
RD
WR/
WRL
Data Sheet
No.
70
71
72
73
74
75
76
77
80
81
Pin Definitions and Functions (cont’d)
Input
Outp.
IO
O
O
O
O
O
I
I
O
I
O
O
O
I
O
I
O
I
O
O
O
Function
Port 4 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. The Port 4 outputs can be configured as
push/pull or open drain drivers. The input threshold of Port 4
is selectable (TTL or special).
Port 4 can be used to output the segment address lines and
for serial interface lines:
A16
A17
A18
A19
A20
CAN2_RxD CAN 2 Receive Data Input,
SDL_RxD SDLM Receive Data Input
A21
CAN1_RxD CAN 1 Receive Data Input,
A22
CAN1_TxD CAN 1 Transmit Data Output,
CAN2_TxD CAN 2 Transmit Data Output,
SDL_RxD SDLM Receive Data Input
A23
CAN1_RxD CAN 1 Receive Data Input,
CAN2_TxD CAN 2 Transmit Data Output,
CAN2_RxD CAN 2 Receive Data Input,
SDL_TxD SDLM Transmit Data Output
External Memory Read Strobe. RD is activated for every
external instruction or data read access.
External Memory Write Strobe. In WR-mode this pin is
activated for every external data write access. In WRL-mode
this pin is activated for low byte data write accesses on a
16-bit bus, and for every data write access on an 8-bit bus.
See WRCFG in register SYSCON for mode selection.
Least Significant Segment Address Line
Segment Address Line
Segment Address Line
Segment Address Line
Segment Address Line,
Segment Address Line,
Segment Address Line,
Most Significant Segment Address Line,
10
1)
C161CS/JC/JI-32R
C161CS/JC/JI-L
(C161CS/JC)
(C161CS/JC)
(C161CS/JC)
(C161JC/JI)
(C161JC/JI)
(C161JC/JI)
V3.0, 2001-01
(C161CS)
(C161CS)
(C161CS)
(C161CS)