PIC24HJ32GP202-I/MM Microchip Technology, PIC24HJ32GP202-I/MM Datasheet - Page 44
![IC PIC MCU FLASH 32K 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC24HJ32GP202-I/MM
Manufacturer Part Number
PIC24HJ32GP202-I/MM
Description
IC PIC MCU FLASH 32K 28QFN
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ32GP202-ISO.pdf
(272 pages)
3.PIC24HJ32GP202-ISO.pdf
(8 pages)
4.PIC24HJ32GP202-ISO.pdf
(12 pages)
5.PIC24HJ32GP204-IML.pdf
(244 pages)
Specifications of PIC24HJ32GP202-I/MM
Program Memory Type
FLASH
Program Memory Size
32KB (11K x 24)
Package / Case
28-QFN
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
2 KB
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM300027
Minimum Operating Temperature
- 40 C
On-chip Adc
10-ch x 12-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC24HJ12GP201-ISO PDF datasheet
- PIC24HJ32GP202-ISO PDF datasheet #2
- PIC24HJ32GP202-ISO PDF datasheet #3
- PIC24HJ32GP202-ISO PDF datasheet #4
- PIC24HJ32GP204-IML PDF datasheet #5
- Current page: 44 of 244
- Download datasheet (4Mb)
PIC24HJ32GP202/204 and PIC24HJ16GP304
4.2
The PIC24HJ32GP202/204 and PIC24HJ16GP304
Flash program memory array is organized into rows of
64 instructions or 192 bytes. RTSP allows the user
application to erase a page of memory, which consists
of eight rows (512 instructions) at a time, and to pro-
gram one row or one word at a time. The 8-row erase
pages and single row write rows are edge-aligned from
the beginning of program memory, on boundaries of
1536 bytes and 192 bytes, respectively.
The program memory implements holding buffers that
can contain 64 instructions of programming data. Prior
to the actual programming operation, the write data
must be loaded into the buffers sequentially. The
instruction words loaded must always be from a group
of 64 boundary.
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWT instructions
to load the buffers. Programming is performed by set-
ting the control bits in the NVMCON register. A total of
64 TBLWTL and TBLWTH instructions are required to
load the instructions.
All table write operations are single-word writes (two
instruction cycles) because only the buffers are written.
A programming cycle is required for programming each
row.
DS70289A-page 42
RTSP Operation
Preliminary
4.3
Two SFRs are used to read and write the program
Flash memory:
• NVMCON: Flash Memory Control Register
• NVMKEY: Non-Volatile Memory Key Register
The NVMCON register (Register 4-1) controls which
blocks need to be erased, which memory type is to be
programmed and the start of the programming cycle.
NVMKEY (Register 4-2) is a write-only register that is
used for write protection. To start a programming or
erase sequence, the user application must consecu-
tively write 55h and AAh to the NVMKEY register. Refer
to Section 4.4 “Programming Operations” for further
details.
4.4
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. A programming operation is nominally 4 ms in
duration and the processor stalls (waits) until the oper-
ation is finished. Setting the WR bit (NVMCON<15>)
starts the operation, and the WR bit is automatically
cleared when the operation is finished.
Control Registers
Programming Operations
© 2007 Microchip Technology Inc.
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