PIC24HJ32GP202-I/MM Microchip Technology, PIC24HJ32GP202-I/MM Datasheet - Page 49
![IC PIC MCU FLASH 32K 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC24HJ32GP202-I/MM
Manufacturer Part Number
PIC24HJ32GP202-I/MM
Description
IC PIC MCU FLASH 32K 28QFN
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ32GP202-ISO.pdf
(272 pages)
3.PIC24HJ32GP202-ISO.pdf
(8 pages)
4.PIC24HJ32GP202-ISO.pdf
(12 pages)
5.PIC24HJ32GP204-IML.pdf
(244 pages)
Specifications of PIC24HJ32GP202-I/MM
Program Memory Type
FLASH
Program Memory Size
32KB (11K x 24)
Package / Case
28-QFN
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
2 KB
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM300027
Minimum Operating Temperature
- 40 C
On-chip Adc
10-ch x 12-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC24HJ12GP201-ISO PDF datasheet
- PIC24HJ32GP202-ISO PDF datasheet #2
- PIC24HJ32GP202-ISO PDF datasheet #3
- PIC24HJ32GP202-ISO PDF datasheet #4
- PIC24HJ32GP204-IML PDF datasheet #5
- Current page: 49 of 244
- Download datasheet (4Mb)
5.0
The Reset module combines all Reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
• POR: Power-on Reset
• BOR: Brown-out Reset
• MCLR: Master Clear Pin Reset
• SWR: RESET Instruction
• WDTO: Watchdog Timer Reset
• TRAPR: Trap Conflict Reset
• IOPUWR: Illegal Opcode, Uninitialized W Regis-
• CM: Configuration Mismatch Reset
Figure 5-1 shows the simplified block diagram of the
Reset module.
FIGURE 5-1:
© 2007 Microchip Technology Inc.
Note:
ter Reset, and Security Reset
RESETS
This data sheet summarizes the features
of
PIC24HJ16GP304 devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”.
PIC24HJ32GP202/204 and PIC24HJ16GP304
MCLR
the
V
DD
Uninitialized W Register
Configuration Mismatch
RESET SYSTEM BLOCK DIAGRAM
PIC24HJ32GP202/204
Regulator
RESET Instruction
Internal
Sleep or Idle
Illegal Opcode
Module
WDT
Trap Conflict
V
DD
Detect
Glitch Filter
Rise
and
Preliminary
BOR
POR
Any active source of Reset makes the SYSRST signal
active. Many registers associated with the CPU and
peripherals are forced to a known Reset state. Most
registers are unaffected by a Reset; their status is
unknown on POR and unchanged by all other Resets.
All types of device Reset will set a corresponding status
bit in the RCON register to indicate the type of Reset
(see Register 5-1). A POR will clear all bits, except for
the POR bit (RCON<0>), that are set. The user appli-
cation can set or clear any bit at any time during code
execution. The RCON bits only serve as status bits.
Setting a particular Reset status bit in software does
not cause a device Reset to occur.
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this manual.
Note:
Note:
Refer to the specific peripheral or CPU
section of this manual for register Reset
states.
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
SYSRST
DS70289A-page 47
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