T89C5115-TISUM Atmel, T89C5115-TISUM Datasheet - Page 59
T89C5115-TISUM
Manufacturer Part Number
T89C5115-TISUM
Description
IC 8051 MCU FLASH 16K 28SOIC
Manufacturer
Atmel
Series
89Cr
Datasheet
1.T89C5115-RATIM.pdf
(113 pages)
Specifications of T89C5115-TISUM
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
20
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
89C5115-TISUM
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Registers
4128G–8051–02/08
Table 37. TCON Register
TCON (S:88h)
Timer/Counter Control Register
Reset Value = 0000 0000b
Number
TF1
Bit
7
7
6
5
4
3
2
1
0
Mnemonic Description
TR1
TF1
TR1
TF0
TR0
Bit
IE1
IE0
IT1
IT0
6
Timer 1 Overflow Flag
Cleared by hardware when processor vectors to interrupt routine.
Set by hardware on Timer/Counter overflow, when Timer 1 register overflows.
Timer 1 Run Control bit
Clear to turn off Timer/Counter 1.
Set to turn on Timer/Counter 1.
Timer 0 Overflow Flag
Cleared by hardware when processor vectors to interrupt routine.
Set by hardware on Timer/Counter overflow, when Timer 0 register overflows.
Timer 0 Run Control bit
Clear to turn off Timer/Counter 0.
Set to turn on Timer/Counter 0.
Interrupt 1 Edge Flag
Cleared by hardware when interrupt is processed if edge-triggered (See IT1).
Set by hardware when external interrupt is detected on INT1# pin.
Interrupt 1 Type Control bit
Clear to select low level active (level triggered) for external interrupt 1 (INT1#).
Set to select falling edge active (edge triggered) for external interrupt 1.
Interrupt 0 Edge Flag
Cleared by hardware when interrupt is processed if edge-triggered (See IT0).
Set by hardware when external interrupt is detected on INT0# pin.
Interrupt 0 Type Control bit
Clear to select low level active (level triggered) for external interrupt 0 (INT0#).
Set to select falling edge active (edge triggered) for external interrupt 0.
TF0
5
TR0
4
IE1
3
IT1
2
IE0
1
IT0
0
59
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