PIC18LF4685-I/P Microchip Technology, PIC18LF4685-I/P Datasheet - Page 120
![IC PIC MCU FLASH 48KX16 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18LF4685-I/P
Manufacturer Part Number
PIC18LF4685-I/P
Description
IC PIC MCU FLASH 48KX16 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PCM18XT0.pdf
(484 pages)
3.PIC18F2221-ISO.pdf
(46 pages)
4.PIC18F2682-ISP.pdf
(6 pages)
5.PIC18F2682-ISP.pdf
(4 pages)
Specifications of PIC18LF4685-I/P
Core Size
8-Bit
Program Memory Size
96KB (48K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
PIC18
No. Of I/o's
36
Eeprom Memory Size
1024Byte
Ram Memory Size
3.25KB
Cpu Speed
40MHz
No. Of Timers
4
Package
40PDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
44
Interface Type
CAN/I2C/SPI/USART
On-chip Adc
11-chx10-bit
Number Of Timers
4
Core
PIC
Processor Series
PIC18LF
Maximum Clock Frequency
40 MHz
Data Ram Size
3.25 KB
Mounting Style
Through Hole
A/d Bit Size
10 bit
A/d Channels Available
11
Height
4.95 mm
Length
53.21 mm
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2 V
Width
14.73 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF4685-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18LF4685-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PCM18XT0 PDF datasheet #2
- PIC18F2221-ISO PDF datasheet #3
- PIC18F2682-ISP PDF datasheet #4
- PIC18F2682-ISP PDF datasheet #5
- Current page: 120 of 484
- Download datasheet (9Mb)
PIC18F2682/2685/4682/4685
9.2
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are two Peripheral Interrupt
Request (Flag) registers (PIR1, PIR2).
REGISTER 9-4:
DS39761C-page 120
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
PSPIF
R/W-0
PIR Registers
(1)
This bit is reserved on PIC18F2682/2685 devices; always maintain this bit clear.
PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
RCIF: EUSART Receive Interrupt Flag bit
1 = The EUSART receive buffer, RCREG, is full (cleared when RCREG is read)
0 = The EUSART receive buffer is empty
TXIF: EUSART Transmit Interrupt Flag bit
1 = The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written)
0 = The EUSART transmit buffer is full
SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
R/W-0
ADIF
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
W = Writable bit
‘1’ = Bit is set
RCIF
R-0
TXIF
R-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SSPIF
R/W-0
Note 1: Interrupt flag bits are set when an interrupt
2: User software should ensure the appropri-
(1)
condition occurs regardless of the state of
its corresponding enable bit or the global
interrupt enable bit, GIE (INTCON<7>).
ate interrupt flag bits are cleared prior to
enabling an interrupt and after servicing
that interrupt.
CCP1IF
R/W-0
© 2009 Microchip Technology Inc.
x = Bit is unknown
TMR2IF
R/W-0
TMR1IF
R/W-0
bit 0
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