PIC18LF4685-I/P Microchip Technology, PIC18LF4685-I/P Datasheet - Page 141

• Manufacturer Part Number: PIC18LF4685-I/P
• Description: IC PIC MCU FLASH 48KX16 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF4685-I/P

• Core Size: 8-Bit
• Program Memory Size: 96KB (48K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3.25KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Package: 40PDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 44
• Interface Type: CAN/I2C/SPI/USART
• On-chip Adc: 11-chx10-bit
• Number Of Timers: 4
• Core: PIC
• Processor Series: PIC18LF
• Maximum Clock Frequency: 40 MHz
• Data Ram Size: 3.25 KB
• Mounting Style: Through Hole
• A/d Bit Size: 10 bit
• A/d Channels Available: 11
• Height: 4.95 mm
• Length: 53.21 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Width: 14.73 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TABLE 10-7:
© 2009 Microchip Technology Inc.
RD0/PSP0/
C1IN+
RD1/PSP1/
C1IN-
RD2/PSP2/
C2IN+
RD3/PSP3/
C2IN-
RD4/PSP4/
ECCP1/P1A
RD5/PSP5/
P1B
RD6/PSP6/
P1C
RD7/PSP7/
P1D
Legend:
Pin Name
OUT = Output; IN = Input; ANA = Analog Signal; DIG = Digital Output; ST = Schmitt Buffer Input; TTL = TTL Buffer Input
RD0
PSP0
C1IN+
RD1
PSP1
C1IN-
RD2
PSP2
C2IN+
RD3
PSP3
C2IN-
RD4
PSP4
ECCP1
P1A
RD5
PSP5
P1B
RD6
PSP6
P1C
RD7
PSP7
P1D
Function
PORTD I/O SUMMARY
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
I/O
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
TRIS Buffer
0
1
x
x
1
0
1
x
x
1
0
1
x
x
1
0
1
x
x
1
0
1
x
x
0
1
0
0
1
X
x
0
0
1
x
x
0
0
1
x
x
0
ANA Comparator 1 positive input B. Default on POR. This analog input overrides the
ANA Comparator 1 negative input. Default on POR. This analog input overrides the
ANA Comparator 2 positive input. Default on POR. This analog input overrides the digital
ANA Comparator 2 negative input. Default input on POR. This analog input overrides the
DIG
DIG
TTL
DIG
DIG
TTL
DIG
DIG
TTL
DIG
DIG
TTL
DIG
DIG
TTL
DIG
DIG
DIG
DIG
TTL
DIG
DIG
DIG
TTL
DIG
DIG
DIG
TTL
DIG
ST
ST
ST
ST
ST
ST
ST
ST
ST
LATD<0> data output.
PORTD<0> data input.
Parallel Slave Port (PSP) data output (overrides the TRIS<0> control when enabled).
Parallel Slave Port (PSP) data input (overrides the TRIS<0> control when enabled).
digital input (read as clear – low level).
LATD<1> data output.
PORTD<1> data input.
Parallel Slave Port (PSP) data output (overrides the TRIS<1> control when enabled).
Parallel Slave Port (PSP) data input (overrides the TRIS<1> control when enabled).
digital input (read as clear – low level).
LATD<2> data output.
PORTD<2> data input.
Parallel Slave Port (PSP) data output (overrides the TRIS<2> control when enabled).
Parallel Slave Port (PSP) data input (overrides the TRIS<2> control when enabled).
input (read as clear – low level).
LATD<3> data output.
PORTD<3> data input.
Parallel Slave Port (PSP) data output (overrides the TRIS<3> control when enabled).
Parallel Slave Port (PSP) data input (overrides the TRIS<3> control when enabled).
digital input (read as clear – low level).
LATD<4> data output.
PORTD<4> data input.
Parallel Slave Port (PSP) data output (overrides the TRIS<4> control when enabled).
Parallel Slave Port (PSP) data input (overrides the TRIS<4> control when enabled).
ECCP1 compare output.
ECCP1 capture input.
ECCP1 Enhanced PWM output, channel A.
LATD<5> data output.
PORTD<5> data input.
Parallel Slave Port (PSP) data output (overrides the TRIS<5> control when enabled).
Parallel Slave Port (PSP) data input (overrides the TRIS<5> control when enabled).
ECCP1 Enhanced PWM output, channel B.
LATD<6> data output.
PORTD<6> data input.
Parallel Slave Port (PSP) data output (overrides the TRIS<6> control when enabled).
Parallel Slave Port (PSP) data input (overrides the TRIS<6> control when enabled).
ECCP1 Enhanced PWM output, channel C.
LATD<7> data output.
PORTD<7> data input.
Parallel Slave Port (PSP) data output (overrides the TRIS<7> control when enabled).
Parallel Slave Port (PSP) data input (overrides the TRIS<7> control when enabled).
ECCP1 Enhanced PWM output, channel D.
PIC18F2682/2685/4682/4685
Description
DS39761C-page 141