EZ80F91NAA50SG Zilog, EZ80F91NAA50SG Datasheet - Page 255

• Manufacturer Part Number: EZ80F91NAA50SG
• Description: IC ACCLAIM MCU 256KB 144BGA
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91NAA50SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LBGA
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG, eZ80F910200KITG
• Minimum Operating Temperature: 0 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4566

Table 136. ZDI Break Control Register
Address Space)
PS027001-0707
Bit
Reset
CPU Access
Note: W = Write Only.
Bit
Position
7
brk_next
6
brk_addr3
5
brk_addr2
4
brk_addr1
3
brk_addr0
Value Description
0
1
0
1
0
1
0
1
0
1
W
7
0
The ZDI break on the next CPU instruction is disabled.
Clearing this bit releases the CPU from its current BREAK
condition.
The ZDI break on the next CPU instruction is enabled. The
CPU uses multibyte Op Codes and multibyte operands.
Break points only occur on the first Op Code in a multibyte
Op Code instruction. If the ZCL pin is High and the ZDA pin
is Low at the end of RESET, this bit is set to 1 and a break
occurs on the first instruction following the RESET. This bit
is set automatically during ZDI break on address match. A
break is also forced by writing a 1 to this bit.
The ZDI break, upon matching break address 3, is
disabled.
The ZDI break, upon matching break address 3, is
enabled.
The ZDI break, upon matching break address 2, is
disabled.
The ZDI break, upon matching break address 2, is
enabled.
The ZDI break, upon matching break address 1, is
disabled.
The ZDI break, upon matching break address 1, is
enabled.
The ZDI break, upon matching break address 0, is
disabled.
The ZDI break, upon matching break address 0, is
enabled.
W
6
0
W
5
0
(ZDI_BRK_CTL = 10h in the ZDI Write Only Register
W
4
0
W
3
0
W
2
0
W
1
0
Product Specification
W
0
0
Zilog Debug Interface
eZ80F91 ASSP
247