C8051T635-GM Silicon Laboratories Inc, C8051T635-GM Datasheet - Page 37

IC MCU 2KB 20PIN QFN

C8051T635-GM

Manufacturer Part Number
C8051T635-GM
Description
IC MCU 2KB 20PIN QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051T63xr
Datasheets

Specifications of C8051T635-GM

Program Memory Type
OTP
Program Memory Size
2KB (2K x 8)
Package / Case
20-QFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
17
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051T6x
Core
8051
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051T630DK
Minimum Operating Temperature
- 40 C
Package
20QFN EP
Device Core
8051
Family Name
C8051T63x
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1464 - KIT DEV FOR C8051T630 FAMILY
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1463-5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051T635-GM
Manufacturer:
Silicon
Quantity:
750
SFR Definition 6.1. ADC0CF: ADC0 Configuration
SFR Address = 0xBC
Name
Reset
Bit
7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Period Bits.
Type
2
1
0
Bit
AMP0GN0 ADC Gain Control Bit.
AD0LJST
AD08BE
Name
7
1
SAR Conversion clock is derived from system clock by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC4–0. SAR Conversion clock
requirements are given in the ADC specification table.
Note: If the Memory Power Controller is enabled (MPCE = '1'), AD0SC must be set to at least
ADC0 Left Justify Select.
0: Data in ADC0H:ADC0L registers are right-justified.
1: Data in ADC0H:ADC0L registers are left-justified.
Note: The AD0LJST bit is only valid for 10-bit mode (AD08BE = 0).
8-Bit Mode Enable.
0: ADC operates in 10-bit mode (normal).
1: ADC operates in 8-bit mode.
Note: When AD08BE is set to 1, the AD0LJST bit is ignored.
0: Gain = 0.5
1: Gain = 1
AD0SC
6
1
"00001" for proper ADC operation.
=
AD0SC[4:0]
SYSCLK
---------------------- - 1
CLK
R/W
5
1
SAR
Rev. 1.0
4
1
Function
3
1
C8051T630/1/2/3/4/5
AD0LJST
R/W
2
0
AD08BE
R/W
1
0
AMP0GN0
R/W
0
1
37

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