C8051T635-GM Silicon Laboratories Inc, C8051T635-GM Datasheet - Page 76

• Manufacturer Part Number: C8051T635-GM
• Description: IC MCU 2KB 20PIN QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051T63xr

Specifications of C8051T635-GM

• Program Memory Type: OTP
• Program Memory Size: 2KB (2K x 8)
• Package / Case: 20-QFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 17
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051T6x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051T630DK
• Minimum Operating Temperature: - 40 C
• Package: 20QFN EP
• Device Core: 8051
• Family Name: C8051T63x
• Maximum Speed: 25 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1464 - KIT DEV FOR C8051T630 FAMILY
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1463-5

C8051T630/1/2/3/4/5
14. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the C8051T630/1/2/3/4/5's resources and
peripherals. The CIP-51 controller core duplicates the SFRs found in a typical 8051 implementation as well
as implementing additional SFRs used to configure and access the sub-systems unique to the
C8051T630/1/2/3/4/5. This allows the addition of new functionality while retaining compatibility with the
MCS-51™ instruction set. Table 14.1 lists the SFRs implemented in the C8051T630/1/2/3/4/5 device fam-
ily.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are bit-
addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corresponding pages of the data sheet, as indicated in
Table 14.2, for a detailed description of each register.
Table 14.1. Special Function Register (SFR) Memory Map
76
E8 ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2
E0
D8 PCA0CN
D0
C8 TMR2CN
C0 SMB0CN
B8
B0
A8
A0
F8
F0
98
90
88
80
(bit addressable)
SPI0CN
SCON0
TCON
PSW
ACC
0(8)
P2
P1
P0
IP
IE
B
OSCXCN
SPI0CFG
PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2
TMR3CN
REF0CN
SMB0CF
CLKSEL
P0MDIN
IDA0CN
SBUF0
PCA0L
TMOD
XBR0
1(9)
SP
SMB0DAT ADC0GTL ADC0GTH ADC0LTL
TMR2RLL TMR2RLH
TMR3RLL TMR3RLH
SPI0CKR
P1MDIN
OSCICN
EMI0CN
PCA0H
XBR1
DPL
2(A)
TL0
PCA0CPL0 PCA0CPH0
OSCLCN
SPI0DAT
CPT0CN
OSCICL
AMX0P
DPH
3(B)
TL1
Rev. 1.0
P0MDOUT P1MDOUT P2MDOUT
ADC0CF
P0SKIP
IT01CF
TMR2L
TMR3L
TH0
4(C)
CPT0MD
P1SKIP
TMR2H
TMR3H
P0MAT
P1MAT
ADC0L
TOFFL
5(D)
TH1
ADC0LTH
P0MASK
P1MASK
CKCON
ADC0H
TOFFH
IDA0L
EIP1
EIE1
6(E)
PCA0PWM
SMB0ADM
SMB0ADR
VDM0CN
REG0CN
RSTSRC
CPT0MX
IDA0H
PCON
7(F)