MCF5211CAE66 Freescale Semiconductor, MCF5211CAE66 Datasheet - Page 5
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MCF5211CAE66
Manufacturer Part Number
MCF5211CAE66
Description
IC MCU 128K FLASH 66MHZ 64-LQFP
Manufacturer
Freescale Semiconductor
Series
MCF521xr
Datasheet
1.MCF5213CAF80.pdf
(54 pages)
Specifications of MCF5211CAE66
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Processor Series
MCF521x
Core
ColdFire V2
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
I2C/QSPI/UART
Maximum Clock Frequency
66 MHz
Number Of Programmable I/os
56
Number Of Timers
10
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
M52210DEMO, M52211EVB
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 12-bit
Package
64LQFP
Device Core
ColdFire
Family Name
MCF521x
Maximum Speed
66 MHz
For Use With
M5211DEMO - KIT DEMO FOR MCF5211
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5211CAE66
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
1.2
1.2.1
The MCF5213 family includes the following features:
Freescale Semiconductor
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Version 2 ColdFire variable-length RISC processor core
— Static operation
— 32-bit address and data paths on-chip
— Up to 80 MHz processor core frequency
— Sixteen general-purpose, 32-bit data and address registers
— Implements ColdFire ISA_A with extensions to support the user stack pointer register and four new instructions
— Multiply-Accumulate (MAC) unit with 32-bit accumulator to support 16×16 → 32 or 32×32 → 32 operations
— Illegal instruction decode that allows for 68-Kbyte emulation support
System debug support
— Real-time trace for determining dynamic execution path
— Background debug mode (BDM) for in-circuit debugging (DEBUG_B+)
— Real-time debug support, with six hardware breakpoints (4 PC, 1 address and 1 data) configurable into a 1- or
On-chip memories
— 32-Kbyte dual-ported SRAM on CPU internal bus, supporting core and DMA access with standby power supply
— 256 Kbytes of interleaved flash memory supporting 2-1-1-1 accesses
Power management
— Fully static operation with processor sleep and whole chip stop modes
— Rapid response to interrupts from the low-power sleep mode (wake-up feature)
— Clock enable/disable for each peripheral when not used
FlexCAN 2.0B module
— Based on and includes all existing features of the Freescale TouCAN module
— Full implementation of the CAN protocol specification version 2.0B
— Flexible message buffers (MBs), totalling up to 16 message buffers of 0–8 byte data length each, configurable as
— Unused MB space can be used as general purpose RAM space
— Listen-only mode capability
— Content-related addressing
— No read/write semaphores
— Three programmable mask registers: global for MBs 0–13, special for MB14, and special for MB15
— Programmable transmit-first scheme: lowest ID or lowest buffer number
— Time stamp based on 16-bit free-running timer
— Global network time, synchronized by a specific message
— Maskable interrupts
Three universal asynchronous/synchronous receiver transmitters (UARTs)
Features
for improved bit processing (ISA_A+)
2-level trigger
support
– Standard data and remote frames (up to 109 bits long)
– Extended data and remote frames (up to 127 bits long)
– Zero to eight bytes data length
– Programmable bit rate up to 1 Mbit/sec
Rx or Tx, all supporting standard and extended messages
Feature Overview
MCF5213 ColdFire Microcontroller, Rev. 4
Family Configurations
5