M30625FGPGP#U7C Renesas Electronics America, M30625FGPGP#U7C Datasheet - Page 219
![IC M16C MCU FLASH 256K 128LQFP](/photos/12/29/122954/m30625fgpgp_u7c_sml.jpg)
M30625FGPGP#U7C
Manufacturer Part Number
M30625FGPGP#U7C
Description
IC M16C MCU FLASH 256K 128LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(308 pages)
3.M30620SPGPU3C.pdf
(423 pages)
Specifications of M30625FGPGP#U7C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Manufacturer
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 17.21
17.1.2.2
17.1.2.3
(1) When the UFORM Bit in the UiC0 Register = 0 (LSB First)
(2) When the UFORM Bit = 1 (MSB First)
NOTES :
CLK
TXDi
RXDi
CLK
TXDi
RXDi
If a communication error occurs while transmitting or receiving in UART mode, follow the procedures below.
As shown in Figure 17.21, use the UFORM bit in the UiC0 register to select the transfer format. This function is
valid when transfer data is 8 bits long.
1. This applies to the case where the CKPOL bit in the UiC0 register = 0
•
(1) Set the RE bit in the UiC1 register to “0” (reception disabled)
(2) Set the RE bit in the UiC1 register to “1” (reception enabled)
•
(1) Set the SMD2 to SMD0 bits in the UiMR register “000b” (Serial interface disabled)
(2) Set the SMD2 to SMD0 bits in the UiMR register “001b”, “101b”, “110b”.
(3) “1” is written to RE bit in the UiC1 register (transmission enabled), regardless of the TE bit in the UiCi
i
i
Jan 10, 2006
(transmit data output at the falling edge and the receive data taken
in at the rising edge of the transfer clock), the UiLCH bit in the UiC1
register = 0 (no reverse), the STPS bit in the UiMR register = 0
(1 stop bit) and the PRYE bit in the UiMR register = 1 (parity enabled).
Resetting the UiRB register (i=0 to 2)
Resetting the UiTB register (i=0 to 2)
register
Counter Measure for Communication Error Occurs
LSB First/MSB First Select Function
Transfer Format
ST
ST
ST
ST
Page 202 of 390
D0
D0
D7
D7
D1
D1
D6
D6
D2
D2
D5
D5
D3
D3
D4
D4
D4
D4
D3
D3
D5
D5
D2
D2
D6
D6
D1
D1
D7
D7
D0
D0
P
P
P
P
SP
SP
SP
SP
17. Serial Interface
ST : Start bit
P : Parity bit
SP : Stop bit
i = 0 to 2
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