M30625FGPGP#U7C Renesas Electronics America, M30625FGPGP#U7C Datasheet - Page 223
![IC M16C MCU FLASH 256K 128LQFP](/photos/12/29/122954/m30625fgpgp_u7c_sml.jpg)
M30625FGPGP#U7C
Manufacturer Part Number
M30625FGPGP#U7C
Description
IC M16C MCU FLASH 256K 128LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(308 pages)
3.M30620SPGPU3C.pdf
(423 pages)
Specifications of M30625FGPGP#U7C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 17.25
SDAi
SCLi
IICM
IICM2, SWC, ALS, SWC2, SDHI : Bit in UiSMR2 register
STSPSEL, ACKD, ACKC
NOTES :
This diagram applies to the case where the SMD2 to SMD0 bits in the UiMR register = 010b and the IICM bit in the UiSMR register = 1.
i=0 to 2
1. If the IICM bit = 1, the pin can be read even when the PD6_2, PD6_6 or PD7_1 bit = 1 (output mode).
Jan 10, 2006
Noise
Filter
I
Noise
Filter
2
C Mode Block Diagram
ACKD register
Delay
circuit
ACKC=1
IICM=1
IICM=0
Falling edge
detection
Page 206 of 390
UARTi
: Bit in UiSMR register
: Bit in UiSMR4 register
STSPSEL=0
I/O port
Start condition
detection
Stop condition
detection
STSPSEL=1
STSPSEL=0
ACKC=0
STSPSEL=1
D
T
Q
Q
R
SDHI
Arbitration
Port register
Internal clock
External
clock
ALS
SWC2
R
S
(1)
S
R
CLK
control
Q
Start and stop condition generation block
SDA(STSP)
SCL(STSP)
Transmission
register
Reception register
9th bit falling edge
Bus
busy
UARTi
UARTi
UARTi
SWC
9th bit
D
D
T
T
Q
Q
IICM2=1
ACK
IICM=1 and
IICM2=0
IICM2=1
IICM=1 and
IICM2=0
NACK
DMA0, DMA1 request
(UART1: DMA0 only)
UARTi transmit,
NACK interrupt
request
DMA0
(UART0, UART2)
UARTi receive,
ACK interrupt request,
DMA1 request
Start/stop condition detection
interrupt request
17. Serial Interface
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