MC68332ACAG16 Freescale Semiconductor, MC68332ACAG16 Datasheet - Page 109

• Manufacturer Part Number: MC68332ACAG16
• Description: IC MCU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332ACAG16

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Interface Type: SCI, SPI, UART
• Minimum Operating Temperature: - 40 C
• Controller Family/series: 68K
• No. Of I/o's: 15
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Data Ram Size: 2 KB
• Number Of Programmable I/os: 15
• Number Of Timers: 16
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 2KB
• # I/os (max): 15
• Number Of Timers - General Purpose: 16
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MC68332
USER’S MANUAL
MOVE from CCR
MOVE from SR
MOVE to CCR
DIVSL/DIVUL
EORI to CCR
EORI to SR
DIVS/DIVU
LPSTOP
MOVEA
ILLEGAL
MOVEA
MOVE
ROXR
ROXL
EXTB
EORI
RTE
DBcc
EOR
LINK
ROR
EXG
RTD
EXT
JMP
LSR
JSR
LEA
LSL
1
1
1
1
1
#<data>, <ea>
#<data>, CCR
<ea>, Dr : Dq
<ea>, Dr : Dq
#<data>, SR
#<data>, Dn
#<data>, Dn
#<data>, Dn
#<data>, Dn
#<data>, Dn
Dn, <label>
<ea>, <ea>
CCR, <ea>
<ea>, CCR
Freescale Semiconductor, Inc.
SR, <ea>
<ea>, Dn
<ea>, Dq
Dn, <ea>
<ea>, An
An, #<d>
<ea>, An
USP, An
An, USP
#<data>
Rn, Rn
Dn, Dn
Dn, Dn
Dn, Dn
Dn, Dn
Dn, Dn
For More Information On This Product,
Table 5-1 Instruction Set Summary
Í
Í
Í
Í
Í
Í
Í
#<d>
none
none
Dn
Dn
Dn
CENTRAL PROCESSING UNIT
Go to: www.freescale.com
64/32
32/32
32/16
none
none
16, 32
32/32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
16
8
8
16, 32
none
none
none
16
16
32
32
16
16
32
32
16
16
16
16
16
16
16
8
32 : 32
32 : 32
16
32
16: 16
32
32
32
SP – 4
SP – 4
0
Data
Sign extended Destination
Sign extended Destination
C
SSP – 2
illegal instruction vector address
(SP)
X/C
If condition false, then Dn – 1
Source x Destination
X
Destination / Source
Destination / Source
Data x Destination
restore stack according to format
SSP – 4
SSP – 2
if Dn (– 1), then PC + d
SP, An
(SP)
Destination
SR; interrupt mask
SP; PC
Source x CCR
SR; SP + 2
Source
Source
(signed or unsigned)
(signed or unsigned)
CCR
Source x SR
SR
SSP; vector offset
Source
PC; SP + 4 + d
SP + 4
<ea>
USP
An
Rn
(SP); SP
SSP; PC
SSP; SR
Destination
Destination
(SP); destination
Destination
Destination
USP
Rn
An
CCR
An
SP; (SP)
SP;
Destination
PC
Destination
Destination
Destination
CCR
SR
An, SP + d
(SSP);
(SSP);
Destination
Destination
EBI; STOP
SP
C
(SSP);
PC
X/C
PC;
PC;
PC
X
PC
0
C
5-11
SP