MC68332AMEH20 Freescale Semiconductor, MC68332AMEH20 Datasheet - Page 43

• Manufacturer Part Number: MC68332AMEH20
• Description: IC MCU 32BIT 20MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332AMEH20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 132-QFP
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Controller Family/series: 68K
• No. Of I/o's: 15
• Ram Memory Size: 2KB
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Data Ram Size: 2 KB
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Package: 132PQFP
• Device Core: ColdFire
• Family Name: 68K/M683xx
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.9 Factory Test Block
SIMTR —System Integration Test Register
SIMTRE —System Integration Test Register (E Clock)
TSTMSRA —Master Shift Register A
TSTMSRB —Master Shift Register B
TSTSC —Test Module Shift Count
TSTRC —Test Module Repetition Count
CREG —Test Module Control Register
DREG —Test Module Distributed Register
MC68332
MC68332TS/D
The test submodule supports scan-based testing of the various MCU modules. It is integrated into the
SIM to support production testing.
Test submodule registers are intended for Motorola use. Register names and addresses are provided
to indicate that these addresses are occupied.
F. The vector number is converted to a vector address.
G. The content of the vector address is loaded into the PC, and the processor transfers control to
1. The dominant interrupt source supplies a vector number and DSACK signals appropriate
2. The AVEC signal is asserted (the signal can be asserted by the dominant interrupt source
3. The bus monitor asserts BERR and the CPU32 generates the spurious interrupt vector
the exception handler routine.
to the access. The CPU32 acquires the vector number.
or the pin can be tied low), and the CPU32 generates an autovector number corresponding
to interrupt priority.
number.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
$YFFA3A
$YFFA02
$YFFA08
$YFFA30
$YFFA32
$YFFA34
$YFFA36
$YFFA38
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