MC68332AMEH20 Freescale Semiconductor, MC68332AMEH20 Datasheet - Page 67

• Manufacturer Part Number: MC68332AMEH20
• Description: IC MCU 32BIT 20MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332AMEH20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 132-QFP
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Controller Family/series: 68K
• No. Of I/o's: 15
• Ram Memory Size: 2KB
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Data Ram Size: 2 KB
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Package: 132PQFP
• Device Core: ColdFire
• Family Name: 68K/M683xx
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FRZ1 — Freeze 1
FRZ0 — Freeze 0
Bits [12:8] — Not Implemented
SUPV — Supervisor/Unrestricted
IARB — Interrupt Arbitration Identification Number
QTEST — QSM Test Register
QILR — QSM Interrupt Levels Register
ILQSPI — Interrupt Level for QSPI
ILSCI — Interrupt Level of SCI
MC68332
MC68332TS/D
RESET:
15
0
0
The system software must stop each submodule before asserting STOP to avoid complications at re-
start and to avoid data corruption. The SCI submodule receiver and transmitter should be disabled, and
the operation should be verified for completion before asserting STOP. The QSPI submodule should be
stopped by asserting the HALT bit in SPCR3 and by asserting STOP after the HALTA flag is set.
FRZ1 determines what action is taken by the QSPI when the FREEZE signal of the IMB is asserted.
FREEZE is asserted whenever the CPU enters the background mode.
Reserved
SUPV defines the assignable QSM registers as either supervisor-only data space or unrestricted data
space.
The IARB field is used to arbitrate between simultaneous interrupt requests of the same priority. Each
module that can generate interrupt requests must be assigned a unique, non-zero IARB field value. Re-
fer to 3.8 Interrupts for more information.
QTEST is used during factory testing of the QSM. Accesses to QTEST must be made while the MCU
is in test mode.
QILR determines the priority level of interrupts requested by the QSM and the vector used when an in-
terrupt is acknowledged.
ILQSPI determines the priority of QSPI interrupts. This field must be given a value between $0 (inter-
rupts disabled) to $7 (highest priority).
ILSCI determines the priority of SCI interrupts. This field must be given a value between $0 (interrupts
disabled) to $7 (highest priority).
If ILQSPI and ILSCI are the same nonzero value, and both submodules simultaneously request inter-
rupt service, QSPI has priority.
0 = Ignore the FREEZE signal on the IMB
1 = Halt the QSPI (on a transfer boundary)
0 = User access
1 = Supervisor access
14
0
0
13
0
ILQSPI
0
Freescale Semiconductor, Inc.
11
For More Information On This Product,
0
10
0
Go to: www.freescale.com
ILSCI
0
8
0
7
QIVR
MOTOROLA
$YFFC02
$YFFC04
0
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