ATTINY5-TSHR Atmel, ATTINY5-TSHR Datasheet - Page 100
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ATTINY5-TSHR
Manufacturer Part Number
ATTINY5-TSHR
Description
IC MCU AVR 512B FLASH SOT-23-6
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY10-TSHR.pdf
(169 pages)
Specifications of ATTINY5-TSHR
Package / Case
SOT-23-6
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
12MHz
Number Of I /o
4
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32 x 8
Program Memory Size
512B (512 x 8)
Data Converters
A/D 4x8b
Oscillator Type
Internal
Peripherals
POR, PWM, WDT
Core Size
8-Bit
Controller Family/series
ATtiny
No. Of I/o's
4
Ram Memory Size
32Byte
Cpu Speed
12MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
ATTINY5x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
32 B
Interface Type
ISP
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
4
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY5-TSHR
Manufacturer:
OMRON
Quantity:
1 500
Part Number:
ATTINY5-TSHR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
14.3.6
14.3.7
14.3.8
100
ATtiny4/5/9/10
Operation
Serial Data Reception
Serial Data Transmission
The TPI physical layer operates synchronously on the TPICLK provided by the external pro-
grammer. The dependency between the clock edges and data sampling or data change is
shown in
Figure 14-6. Data changing and Data sampling.
The TPI physical layer supports two modes of operation: Transmit and Receive. By default, the
layer is in Receive mode, waiting for a start bit. The mode of operation is controlled by the
access layer.
When the TPI physical layer is in receive mode, data reception is started as soon as a start bit
has been detected. Each bit that follows the start bit will be sampled at the rising edge of the
TPICLK and shifted into the shift register until the second stop bit has been received. When the
complete frame is present in the shift register the received data will be available for the TPI
access layer.
There are three possible exceptions in the receive mode: frame error, parity error and break
detection. All these exceptions are signalized to the TPI access layer, which then enters the
error state and puts the TPI physical layer into receive mode, waiting for a BREAK character.
When the TPI physical layer is ready to send a new frame it initiates data transmission by load-
ing the shift register with the data to be transmitted. When the shift register has been loaded with
new data, the transmitter shifts one complete frame out on the TPIDATA line at the transfer rate
given by TPICLK.
If a collision is detected during transmission, the output driver is disabled. The TPI access layer
enters the error state and the TPI physical layer is put into receive mode, waiting for a BREAK
character.
• Frame Error Exception. The frame error exception indicates the state of the stop bit. The
• Parity Error Exception. The parity of the data bits is calculated during the frame reception.
• Break Detection Exception. The Break detection exception is given when a complete frame of
frame error exception is set if the stop bit was read as zero.
After the frame is received completely, the result is compared with the parity bit of the frame.
If the comparison fails the parity error exception is signalized.
all zeros has been received.
Figure
14-6. Data is changed at falling edges and sampled at rising edges.
TPICLK
TPIDATA
SAMPLE
SETUP
8127D–AVR–02/10