ATTINY5-TSHR Atmel, ATTINY5-TSHR Datasheet - Page 85
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ATTINY5-TSHR
Manufacturer Part Number
ATTINY5-TSHR
Description
IC MCU AVR 512B FLASH SOT-23-6
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY10-TSHR.pdf
(169 pages)
Specifications of ATTINY5-TSHR
Package / Case
SOT-23-6
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
12MHz
Number Of I /o
4
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32 x 8
Program Memory Size
512B (512 x 8)
Data Converters
A/D 4x8b
Oscillator Type
Internal
Peripherals
POR, PWM, WDT
Core Size
8-Bit
Controller Family/series
ATtiny
No. Of I/o's
4
Ram Memory Size
32Byte
Cpu Speed
12MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
ATTINY5x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
32 B
Interface Type
ISP
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
4
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY5-TSHR
Manufacturer:
OMRON
Quantity:
1 500
Part Number:
ATTINY5-TSHR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
13.4
8127D–AVR–02/10
Starting a Conversion
Figure 13-1. Analog to Digital Converter Block Schematic
Make sure the ADC is powered by clearing the ADC Power Reduction bit, PRADC, in the Power
Reduction Register, PRR (see
A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC.
This bit stays high as long as the conversion is in progress and will be cleared by hardware
when the conversion is completed. If a different data channel is selected while a conversion is in
progress, the ADC will finish the current conversion before performing the channel change.
Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is
enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is
selected by setting the ADC Trigger Select bits, ADTS in “ADCSRB – ADC Control and Status
Register B”. See
occurs on the selected trigger signal, the ADC prescaler is reset and a conversion is started.
This provides a method of starting conversions at fixed intervals. If the trigger signal still is set
when the conversion completes, a new conversion will not be started. If another positive edge
occurs on the trigger signal during conversion, the edge will be ignored. Note that an interrupt
flag will be set even if the specific interrupt is disabled. A conversion can thus be triggered with-
out causing an interrupt. However, the interrupt flag must be cleared in order to trigger a new
conversion at the next interrupt event.
ADC3
ADC2
ADC1
ADC0
V
CC
8-BIT DATA BUS
DECODER
ADMUX
Table 13-4 on page 96
INPUT
MUX
VREF
ADCSRB
“PRR – Power Reduction Register” on page
TRIGGER
SELECT
8-BIT DAC
for a list of the trigger sources. When a positive edge
PRESCALER
ADCSRA
CONVERSION LOGIC
SAMPLE & HOLD
COMPARATOR
-
+
ATtiny4/5/9/10
26).
ADCL
ADC IRQ
85