ATTINY5-TSHR Atmel, ATTINY5-TSHR Datasheet - Page 42
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ATTINY5-TSHR
Manufacturer Part Number
ATTINY5-TSHR
Description
IC MCU AVR 512B FLASH SOT-23-6
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY10-TSHR.pdf
(169 pages)
Specifications of ATTINY5-TSHR
Package / Case
SOT-23-6
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
12MHz
Number Of I /o
4
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32 x 8
Program Memory Size
512B (512 x 8)
Data Converters
A/D 4x8b
Oscillator Type
Internal
Peripherals
POR, PWM, WDT
Core Size
8-Bit
Controller Family/series
ATtiny
No. Of I/o's
4
Ram Memory Size
32Byte
Cpu Speed
12MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
ATTINY5x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
32 B
Interface Type
ISP
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
4
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY5-TSHR
Manufacturer:
OMRON
Quantity:
1 500
Part Number:
ATTINY5-TSHR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
10.2
10.2.1
42
Ports as General Digital I/O
ATtiny4/5/9/10
Configuring the Pin
The ports are bi-directional I/O ports with optional internal pull-ups.
tional description of one I/O-port pin, here generically called Pxn.
Figure 10-2. General Digital I/O
Note:
Each port pin consists of four register bits: DDxn, PORTxn, PUExn, and PINxn. As shown in
“Register Description” on page
PORTxn bits at the PORTx I/O address, the PUExn bits at the PUEx I/O address, and the PINxn
bits at the PINx I/O address.
Pxn
1. WEx, WRx, WPx, WDx, REx, RRx, RPx, and RDx are common to all pins within the same
port. clk
SLEEP:
clk
I/O
I/O
:
, and SLEEP are common to all ports.
SLEEP CONTROL
I/O CLOCK
SLEEP
51, the DDxn bits are accessed at the DDRx I/O address, the
(1)
SYNCHRONIZER
D
L
Q
Q
D
PINxn
Q
Q
RESET
RESET
RESET
PORTxn
WEx:
REx:
WDx:
RDx:
WRx:
RRx:
RPx:
WPx:
Q
Q
Q
Q
Q
Q
PUExn
DDxn
CLR
CLR
CLR
D
D
D
REx
RRx
WRITE PUEx
READ PUEx
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
WRITE PINx REGISTER
Figure 10-2
WEx
WDx
RDx
RPx
clk
1
0
I/O
WRx
shows a func-
8127D–AVR–02/10
WPx