ATTINY5-TSHR Atmel, ATTINY5-TSHR Datasheet - Page 95
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ATTINY5-TSHR
Manufacturer Part Number
ATTINY5-TSHR
Description
IC MCU AVR 512B FLASH SOT-23-6
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY10-TSHR.pdf
(169 pages)
Specifications of ATTINY5-TSHR
Package / Case
SOT-23-6
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
12MHz
Number Of I /o
4
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32 x 8
Program Memory Size
512B (512 x 8)
Data Converters
A/D 4x8b
Oscillator Type
Internal
Peripherals
POR, PWM, WDT
Core Size
8-Bit
Controller Family/series
ATtiny
No. Of I/o's
4
Ram Memory Size
32Byte
Cpu Speed
12MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
ATTINY5x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
32 B
Interface Type
ISP
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
4
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY5-TSHR
Manufacturer:
OMRON
Quantity:
1 500
Part Number:
ATTINY5-TSHR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
13.12.3
8127D–AVR–02/10
ADCSRB
–
ADC Control and Status Register B
• Bit 4 – ADIF: ADC Interrupt Flag
This bit is set when an ADC conversion completes and the data registers are updated. The ADC
Conversion Complete Interrupt is requested if the ADIE bit is set. ADIF is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by
writing a logical one to the flag.
• Bit 3 – ADIE: ADC Interrupt Enable
When this bit is written to one, the ADC Conversion Complete Interrupt request is enabled.
• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits
These bits determine the division factor between the system clock frequency and the input clock
to the ADC.
Table 13-3.
• Bits 7:3 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bits 2:0 – ADTS2:0: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger
an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion
will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trig-
ger source that is cleared to a trigger source that is set, will generate a positive edge on the
Bit
0x1C
Read/Write
Initial Value
ADPS2
0
0
0
0
1
1
1
1
ADC Prescaler Selections
R
7
–
0
R
6
–
0
ADPS1
0
0
1
1
0
0
1
1
R
5
–
0
R
4
–
0
ADPS0
0
1
0
1
0
1
0
1
R
3
–
0
ADTS2
R/W
2
0
ADTS1
R/W
1
0
ATtiny4/5/9/10
Division Factor
ADTS0
R/W
0
0
128
16
32
64
2
2
4
8
ADCSRB
95