PIC16F526-E/SL Microchip Technology, PIC16F526-E/SL Datasheet - Page 50

IC PIC MCU FLASH 1KX12 14SOIC

PIC16F526-E/SL

Manufacturer Part Number
PIC16F526-E/SL
Description
IC PIC MCU FLASH 1KX12 14SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets

Specifications of PIC16F526-E/SL

Core Size
8-Bit
Program Memory Size
1.5KB (1K x 12)
Core Processor
PIC
Speed
20MHz
Peripherals
POR, WDT
Number Of I /o
11
Program Memory Type
FLASH
Ram Size
67 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 3x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Controller Family/series
PIC16F
No. Of I/o's
12
Eeprom Memory Size
64Byte
Ram Memory Size
67Byte
Cpu Speed
20MHz
No. Of Timers
1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
ICE2000 - EMULATOR MPLAB-ICE 2000 POD
Eeprom Size
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
PIC16F526
8.3.1
This Configuration bit, when unprogrammed (left in the
‘1’ state), enables the external MCLR function. When
programmed, the MCLR function is tied to the internal
V
FIGURE 8-6:
8.4
The PIC16F526 device incorporates an on-chip Power-
on Reset (POR) circuitry, which provides an internal
chip Reset for most power-up situations.
The on-chip POR circuit holds the chip in Reset until
V
ation. To take advantage of the internal POR, program
the RB3/MCLR/V
resistor to V
weak pull-up resistor is implemented using a transistor
(refer to Table 14-5 for the pull-up resistor ranges). This
will eliminate external RC components usually needed
to create a Power-on Reset. A maximum rise time for
V
acteristics” for details.
When the device starts normal operation (exit the
Reset condition), device operating parameters (volt-
age, frequency, temperature,...) must be met to ensure
operation. If these conditions are not met, the device
must be held in Reset until the operating parameters
are met.
A simplified block diagram of the on-chip Power-on
Reset circuit is shown in Figure 8-7.
DS41326E-page 50
DD
DD
DD
MCLRE
RBWU
and the pin is assigned to be a I/O. See Figure 8-6.
has reached a high enough level for proper oper-
is specified. See Section 14.0 “Electrical Char-
Power-on Reset (POR)
MCLR ENABLE
DD
, or program the pin as RB3. An internal
PP
pin as MCLR and tie through a
MCLR SELECT
RB3/MCLR/V
Internal MCLR
PP
The Power-on Reset circuit and the Device Reset
Timer (see Section 8.5 “Device Reset Timer (DRT)”)
circuit are closely related. On power-up, the Reset latch
is set and the DRT is reset. The DRT timer begins
counting once it detects MCLR to be high. After the
time-out period, which is typically 18 ms or 1 ms, it will
reset the Reset latch and thus end the on-chip Reset
signal.
A power-up example where MCLR is held low is shown
in Figure 8-8. V
bringing MCLR high. The chip will actually come out of
Reset T
In Figure 8-9, the on-chip Power-on Reset feature is
being used (MCLR and V
is programmed to be RB3. The V
start-up timer times out and there is no problem in get-
ting a proper Reset. However, Figure 8-10 depicts a
problem situation where V
between when the DRT senses that MCLR is high and
when MCLR and V
too long. In this situation, when the start-up timer times
out, V
chip may not function correctly. For such situations, we
recommend that external RC circuits be used to
achieve longer POR delay times (Figure 8-9).
For additional information, refer to Application Notes
AN522 “Power-Up Considerations” (DS00522) and
AN607 “Power-up Trouble Shooting” (DS00607).
Note:
DD
DRT
has not reached the V
When the device starts normal operation
(exit the Reset condition), device operat-
ing parameters (voltage, frequency, tem-
perature, etc.) must be met to ensure
operation. If these conditions are not met,
the device must be held in Reset until the
operating conditions are met.
msec after MCLR goes high.
DD
is allowed to rise and stabilize before
DD
actually reach their full value, is
 2010 Microchip Technology Inc.
DD
DD
are tied together or the pin
rises too slowly. The time
DD
DD
(min) value and the
is stable before the

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