ATTINY13-20SSQ Atmel, ATTINY13-20SSQ Datasheet - Page 24
![MCU AVR 1KB FLASH 20MHZ 8SOIC GW](/photos/6/50/65032/453-8-soic_sml.jpg)
ATTINY13-20SSQ
Manufacturer Part Number
ATTINY13-20SSQ
Description
MCU AVR 1KB FLASH 20MHZ 8SOIC GW
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY13-20SSQ
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
1KB (512 x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Processor Series
ATTINY1x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
64 B
Interface Type
SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
6
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAKSTK511
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
For Use With
ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Lead Free Status / Rohs Status
Details
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6.1.4
6.2
6.2.1
24
Clock Sources
ATtiny13
ADC Clock – clk
External Clock
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks
in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion
results.
The device has the following clock source options, selectable by Flash fuse bits as shown
below. The clock from the selected source is input to the AVR clock generator, and routed to the
appropriate modules.
Table 6-1.
Note:
The various choices for each clocking option is given in the following sections. When the CPU
wakes up from Power-down or Power-save, the selected clock source is used to time the start-
up, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts
from reset, there is an additional delay allowing the power to reach a stable level before com-
mencing normal operation. The Watchdog Oscillator is used for timing this real-time part of the
start-up time. The number of WDT Oscillator cycles used for each time-out is shown in
2.
Table 6-2.
To drive the device from an external clock source, CLKI should be driven as shown in
2. To run the device on an external clock, the CKSEL fuses must be programmed to “00”.
Figure 6-2.
Device Clocking Option
External Clock (see
Calibrated Internal 4.8/9.6 MHz Oscillator (see
Internal 128 kHz Oscillator (see
ADC
1. For all fuses “1” means unprogrammed while “0” means programmed.
Typ Time-out
Device Clocking Options Select
Number of Watchdog Oscillator Cycles
External Clock Drive Configuration
EXTERNAL
64 ms
4 ms
page
SIGNAL
CLOCK
24)
page
26)
page
25)
CLKI
GND
Number of Cycles
8K (8,192)
512
CKSEL1:0
01, 10
00
11
(1)
2535J–AVR–08/10
Figure 6-
Table 6-
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