ATTINY13-20SSQ Atmel, ATTINY13-20SSQ Datasheet - Page 28
![MCU AVR 1KB FLASH 20MHZ 8SOIC GW](/photos/6/50/65032/453-8-soic_sml.jpg)
ATTINY13-20SSQ
Manufacturer Part Number
ATTINY13-20SSQ
Description
MCU AVR 1KB FLASH 20MHZ 8SOIC GW
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY13-20SSQ
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
1KB (512 x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Processor Series
ATTINY1x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
64 B
Interface Type
SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
6
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAKSTK511
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
For Use With
ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Lead Free Status / Rohs Status
Details
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6.4.2
28
ATtiny13
CLKPR – Clock Prescale Register
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE
bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is
cleared by hardware four cycles after it is written or when the CLKPS bits are written. Rewriting
the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the
CLKPCE bit.
• Bits 6:4 – Res: Reserved Bits
These bits are reserved bits in the ATtiny13 and will always read as zero.
• Bits 3:0 – CLKPS3:0: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal system
clock. These bits can be written run-time to vary the clock frequency to suit the application
requirements. As the divider divides the master clock input to the MCU, the speed of all synchro-
nous peripherals is reduced when a division factor is used. The division factors are given in
Table 6-8 on page
To avoid unintentional changes of clock frequency, a special write procedure must be followed
to change the CLKPS bits:
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is
not interrupted.hee setting. The Application software must ensure that a sufficient division factor
is chosen if the selected clock source has a higher frequency than the maximum frequency of
the device at the present operating conditions. The device is shipped with the CKDIV8 fuse
programmed.
Table 6-8.
Bit
Read/Write
Initial Value
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in
2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
CLKPS3
CLKPR to zero.
0
0
0
0
0
0
0
0
1
Clock Prescaler Select
CLKPCE
R/W
7
0
28.
CLKPS2
0
0
0
0
1
1
1
1
0
R
6
–
0
CLKPS1
R
5
–
0
0
0
1
1
0
0
1
1
0
R
4
–
0
CLKPS0
CLKPS3
R/W
3
0
1
0
1
0
1
0
1
0
CLKPS2
See Bit Description
R/W
2
Clock Division Factor
CLKPS1
R/W
1
128
256
16
32
64
CLKPS0
1
2
4
8
R/W
0
2535J–AVR–08/10
CLKPR
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