ATTINY13-20SSQ Atmel, ATTINY13-20SSQ Datasheet - Page 56
![MCU AVR 1KB FLASH 20MHZ 8SOIC GW](/photos/6/50/65032/453-8-soic_sml.jpg)
ATTINY13-20SSQ
Manufacturer Part Number
ATTINY13-20SSQ
Description
MCU AVR 1KB FLASH 20MHZ 8SOIC GW
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY13-20SSQ
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
1KB (512 x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Processor Series
ATTINY1x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
64 B
Interface Type
SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
6
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAKSTK511
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
For Use With
ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Lead Free Status / Rohs Status
Details
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- Download datasheet (3Mb)
10.4
10.4.1
10.4.2
10.4.3
56
Register Description
ATtiny13
MCUCR – MCU Control Register
PORTB – Port B Data Register
DDRB – Port B Data Direction Register
Table 10-5.
• Bits 7, 2– Res: Reserved Bits
These bits are reserved bits in the ATtiny13 and will always read as zero.
• Bit 6 – PUD: Pull-up Disable
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and
PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See
figuring the Pin” on page 49
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
PB2/SCK/ADC1/
T0/PCINT2
0
0
0
0
0
0
0
PCINT2 • PCIE + ADC1D
ADC1D
T0/INT0/
PCINT2 Input
ADC1 Input
Overriding Signals for Alternate Functions in PB2:PB0
R
7
–
0
R
R
7
–
0
7
–
0
PUD
R/W
R
R
6
–
0
6
–
0
6
0
for more details about this feature.
PORTB5
DDB5
R/W
R/W
R/W
5
5
0
0
SE
5
0
PB1/MISO/AIN1/
OC0B/INT0/PCINT1
0
0
0
0
OC0B Enable
OC0B
0
PCINT1 • PCIE + AIN1D
AIN1D
PCINT1 Input
Analog Comparator
Negative Input
PORTB4
DDB4
R/W
R/W
4
0
4
0
SM1
R/W
4
0
PORTB3
DDB3
R/W
R/W
3
0
3
0
SM0
R/W
3
0
PORTB2
DDB2
R/W
R/W
2
0
2
0
R
2
–
0
PB0/MOSI/AIN0/
AREF/OC0A/PCINT0
0
0
0
0
OC0A Enable
OC0A
0
PCINT0 • PCIE + AIN0D
AIN0D
PCINT0 Input
Analog Comparator Positive
Input
PORTB1
DDB1
R/W
R/W
ISC01
R/W
1
0
1
0
1
0
PORTB0
DDB0
ISC00
R/W
R/W
R/W
0
0
0
0
0
0
2535J–AVR–08/10
MCUCR
PORTB
DDRB
“Con-
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