PIC18F65J15T-I/PT Microchip Technology, PIC18F65J15T-I/PT Datasheet - Page 334

IC PIC MCU FLASH 24KX16 64TQFP

PIC18F65J15T-I/PT

Manufacturer Part Number
PIC18F65J15T-I/PT
Description
IC PIC MCU FLASH 24KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F65J15T-I/PT

Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
48KB (24K x 16)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
For Use With
MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
PIC18F65J15T-I/PT
PIC18F65J15T-I/PTTR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F65J15T-I/PT
Manufacturer:
FAIRCHILD
Quantity:
100
Part Number:
PIC18F65J15T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC18F87J10 FAMILY
TBLWT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
DS39663F-page 332
Table Write
TBLWT ( *; *+; *-; +*)
None
if TBLWT*,
(TABLAT) → Holding Register,
TBLPTR – No Change;
if TBLWT*+,
(TABLAT) → Holding Register,
(TBLPTR) + 1 → TBLPTR;
if TBLWT*-,
(TABLAT) → Holding Register,
(TBLPTR) – 1 → TBLPTR;
if TBLWT+*,
(TBLPTR) + 1 → TBLPTR,
(TABLAT) → Holding Register
None
This instruction uses the 3 LSBs of
TBLPTR to determine which of the
8 holding registers the TABLAT is written
to. The holding registers are used to
program the contents of Program Memory
(P.M.). (Refer to Section 6.0 “Memory
Organization” for additional details on
programming Flash memory.)
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory.
TBLPTR has a 2-Mbyte address range.
The LSb of the TBLPTR selects which
byte of the program memory location to
access.
The TBLWT instruction can modify the
value of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
1
2
operation
Decode
0000
TBLPTR[0] = 0: Least Significant Byte
TBLPTR[0] = 1: Most Significant Byte
Q1
No
operation
operation
TABLAT)
(Read
0000
Q2
No
No
of Program Memory
Word
of Program Memory
Word
operation
operation
0000
Q3
No
No
nn=0 *
operation
operation
Register)
(Write to
Holding
=1 *+
=2 *-
=3 +*
11nn
Q4
No
No
TBLWT
Example 1:
Example 2:
Before Instruction
After Instructions (table write completion)
Before Instruction
After Instruction (table write completion)
TABLAT
TBLPTR
HOLDING REGISTER
(00A356h)
TABLAT
TBLPTR
HOLDING REGISTER
(00A356h)
TABLAT
TBLPTR
HOLDING REGISTER
(01389Ah)
HOLDING REGISTER
(01389Bh)
TABLAT
TBLPTR
HOLDING REGISTER
(01389Ah)
HOLDING REGISTER
(01389Bh)
Table Write (Continued)
TBLWT *+;
TBLWT +*;
© 2009 Microchip Technology Inc.
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55h
00A356h
FFh
55h
00A357h
55h
34h
01389Ah
FFh
FFh
34h
01389Bh
FFh
34h

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