PIC18F65J15T-I/PT Microchip Technology, PIC18F65J15T-I/PT Datasheet - Page 39

• Manufacturer Part Number: PIC18F65J15T-I/PT
• Description: IC PIC MCU FLASH 24KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J15T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• For Use With: MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: PIC18F65J15T-I/PT; PIC18F65J15T-I/PTTR

3.7
When PRI_IDLE mode is selected, the designated
primary oscillator continues to run without interruption.
For all other power-managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin if used by the oscillator) will stop oscillating.
In
SEC_IDLE), the Timer1 oscillator is operating and
providing the device clock. The Timer1 oscillator may
also run in all power-managed modes if required to
clock Timer1 or Timer3.
In RC_RUN and RC_IDLE modes, the internal oscilla-
tor provides the device clock source. The 31 kHz
INTRC output can be used directly to provide the clock
and may be enabled to support various special
features, regardless of the power-managed mode (see
Section 24.2 “Watchdog Timer (WDT)” through
Section 24.5 “Fail-Safe Clock Monitor” for more
information on WDT, Fail-Safe Clock Monitor and
Two-Speed Start-up).
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTRC is required to support WDT operation. The
TABLE 3-3:
© 2009 Microchip Technology Inc.
EC, ECPLL
HS, HSPLL
Note:
secondary
Oscillator Mode
Effects of Power-Managed Modes
on the Various Clock Sources
See Table 5-2 in Section 5.0 “Reset” for time-outs due to Sleep and MCLR Reset.
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
clock
modes
Floating, pulled by external clock
Feedback inverter disabled at quiescent
voltage level
(SEC_RUN
OSC1 Pin
and
PIC18F87J10 FAMILY
Timer1 oscillator may be operating to support a
Real-Time Clock. Other features may be operating that
do not require a device clock source (i.e., MSSP slave,
PSP, INTx pins and others). Peripherals that may add
significant
Section 27.2 “DC Characteristics: Power-Down and
Supply Current”.
3.8
Power-up delays are controlled by two timers, so that
no external Reset circuitry is required for most applica-
tions. The delays ensure that the device is kept in
Reset until the device power supply is stable under
normal circumstances and the primary clock is operat-
ing and stable. For additional information on power-up
delays, see Section 5.5 “Power-up Timer (PWRT)”.
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (parameter 33,
Table 27-12). It is always enabled.
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (HS modes). The OST does
this by counting 1024 oscillator cycles before allowing
the oscillator to clock the device.
There is a delay of interval, T
Table 27-12), following POR, while the controller
becomes ready to execute instructions.
Power-up Delays
At logic low (clock/4 output)
Feedback inverter disabled at quiescent
voltage level
current
consumption
OSC2 Pin
CSD
DS39663F-page 37
are
(parameter 38,
listed
in