PIC18F65J15T-I/PT Microchip Technology, PIC18F65J15T-I/PT Datasheet - Page 44

• Manufacturer Part Number: PIC18F65J15T-I/PT
• Description: IC PIC MCU FLASH 24KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J15T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• For Use With: MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: PIC18F65J15T-I/PT; PIC18F65J15T-I/PTTR

PIC18F87J10 FAMILY
4.2.3
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator; the primary clock is
shut down. This mode provides the best power conser-
vation of all the Run modes while still executing code.
It works well for user applications which are not highly
timing sensitive or do not require high-speed clocks at
all times.
This mode is entered by setting the SCS bits to ‘11’.
When the clock source is switched to the INTRC (see
Figure 4-3), the primary oscillator is shut down and the
OSTS bit is cleared.
FIGURE 4-3:
FIGURE 4-4:
DS39663F-page 42
Peripheral
Program
Counter
INTRC
OSC1
Note 1: T
Clock
Clock
RC_RUN MODE
CPU Clock
CPU
PLL Clock
Peripheral
Program
Counter
INTRC
Output
OSC1
Clock
Q1
OST
SCS<1:0> Bits Changed
Q2
= 1024 T
TRANSITION TIMING TO RC_RUN MODE
TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
PC
Q3
Q4
OSC
; T
Q1
Q1
PLL
T
1
= 2 ms (approx). These intervals are not shown to scale.
OST
(1)
PC
Q2
2
Clock Transition
3
T
OSTS Bit Set
PLL
Q3
(1)
PC + 2
Q4
n-1
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTRC
while the primary clock is started. When the primary
clock becomes ready, a clock switch to the primary
clock occurs (see Figure 4-4). When the clock switch is
complete, the OSTS bit is set and the primary clock is
providing the device clock. The IDLEN and SCS bits
are not affected by the switch. The INTRC source will
continue to run if either the WDT or the Fail-Safe Clock
Monitor is enabled.
n
Q1
1
Transition
2
Clock
n-1 n
Q2
PC + 2
Q3
Q2
Q4
© 2009 Microchip Technology Inc.
Q3 Q4
Q1
Q1
PC + 4
Q2
Q2
PC + 4
Q3
Q3