PIC16F819-I/SOTSL Microchip Technology, PIC16F819-I/SOTSL Datasheet - Page 299
![IC PIC MCU FLASH 2KX14 18SOIC](/photos/6/76/67656/150-18-soic_sml.jpg)
PIC16F819-I/SOTSL
Manufacturer Part Number
PIC16F819-I/SOTSL
Description
IC PIC MCU FLASH 2KX14 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F818-ISO.pdf
(176 pages)
4.PIC16F818-ISO.pdf
(6 pages)
5.PIC16F818-ISO.pdf
(8 pages)
6.PIC16F818-ISO.pdf
(8 pages)
Specifications of PIC16F819-I/SOTSL
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
18-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC16F818-ISO PDF datasheet #4
- PIC16F818-ISO PDF datasheet #5
- PIC16F818-ISO PDF datasheet #6
- Current page: 299 of 688
- Download datasheet (3Mb)
17.4.1.3
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
CKP (SSPCON1<4>)
SDA
SCL
SSPIF
1997 Microchip Technology Inc.
BF (SSPSTAT<0>)
SSPOV (SSPCON1<6>)
S
S
Slave Transmission
A7 A6 A5 A4 A3 A2 A1
1
A7
2
1
Data in
sampled
Receiving Address
3
A6
2
When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit
of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The
ACK pulse will be sent on the ninth bit, and the SCL pin is held low. The transmit data must be
loaded into the SSPBUF register, which also loads the SSPSR register. Then the SCL pin should
be enabled by setting the CKP bit (SSPCON1<4>). The master should monitor the SCL pin prior
to asserting another clock pulse. The slave devices may be holding off the master by stretching
the clock. The eight data bits are shifted out on the falling edge of the SCL input. This ensures
that the SDA signal is valid during the SCL high time
An SSP interrupt is generated for each data transfer byte. The SSPIF flag bit must be cleared in
software, and the SSPSTAT register is used to determine the status of the byte transfer. The
SSPIF flag bit is set on the falling edge of the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the master-receiver is latched on the rising edge of
the ninth SCL input pulse. If the SDA line was high (not ACK), then the data transfer is complete.
When the not ACK is latched by the slave, the slave logic is reset and the slave then monitors for
another occurrence of the START bit. If the SDA line was low (ACK), the transmit data must be
loaded into the SSPBUF register, which also loads the SSPSR register. Then the SCL pin should
be enabled by setting the CKP bit.
Figure 17-12: I
Figure 17-13: I
4
A5
Receiving Address
3
5
A4
6
4
7
A3
5
R/W=0
8
A2
2
2
6
C Slave Mode Waveforms for Reception (7-bit Address)
C Slave Mode Waveforms for Transmission (7-bit Address)
ACK
9
A1
7
D7
1
D6
R/W = 1
2
8
SSPBUF register is read
Cleared in software
Preliminary
Receiving Data
D5
3
9
ACK
D4
Bit SSPOV is set because the SSPBUF register is still full.
responds to SSPIF
4
while CPU
SCL held low
D3
5
D2
6
D1
7
D7
1
SSPBUF is written in software
D0
8
Section 17. MSSP
ACK
D6
9
cleared in software
2
Set bit after writing to SSPBUF
(the SSPBUF must be written-to
before the CKP bit can be set)
D7
(Figure
1
D5
3
D6
2
D4
4
D5
Receiving Data
3
17-13).
Transmitting Data
D3
D4
4
5
ACK is not sent.
D3
D2
5
6
D2
6
From SSP interrupt
service routine
D1
7
D1
7
DS31017A-page 17-23
D0
8
D0
8
R/W = 0
ACK
ACK
9
9
transfer
Bus Master
terminates
P
P
17
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