PIC16F819-I/SOTSL Microchip Technology, PIC16F819-I/SOTSL Datasheet - Page 451
![IC PIC MCU FLASH 2KX14 18SOIC](/photos/6/76/67656/150-18-soic_sml.jpg)
PIC16F819-I/SOTSL
Manufacturer Part Number
PIC16F819-I/SOTSL
Description
IC PIC MCU FLASH 2KX14 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F818-ISO.pdf
(176 pages)
4.PIC16F818-ISO.pdf
(6 pages)
5.PIC16F818-ISO.pdf
(8 pages)
6.PIC16F818-ISO.pdf
(8 pages)
Specifications of PIC16F819-I/SOTSL
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
18-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC16F818-ISO PDF datasheet #4
- PIC16F818-ISO PDF datasheet #5
- PIC16F818-ISO PDF datasheet #6
- Current page: 451 of 688
- Download datasheet (3Mb)
24.3.2
24.3.3
24.3.4
24.3.5
24.3.6
1997 Microchip Technology Inc.
Sleep Operation
Effects of a Reset
Slope A/D Comparator
Analog MUX
Programmable Current Source
The Slope A/D may operate when the device is in Sleep mode. For the Slope A/D to do a con-
version during Sleep mode, the Slope A/D module must have a device clock. For a clock to be
present the OSCOFF bit must be cleared before going to SLEEP. Also the REFOFF and ADOFF
bits must be cleared to ensure that the results reflect the voltage on the input channel. By doing
an A/D conversion during Sleep mode, the result has improved accuracy due to a reduction of
system noise.
When the device clock is disabled, the Slope A/D Timer (ADTMRH:ADTMRL) stops increment-
ing. Even if the Slope A/D module is not disabled, the slope A/D cannot wake-up the device. This
is because the ADCIF bit cannot be set, which is one of the control bits used to wake the device
from SLEEP mode. When the device awakes, if the comparator value has tripped, the capture
and interrupt will occur. The value in the ADCAP registers is meaningless.
For maximum power savings, all analog components of the Slope A/D module should be disabled
(no conversion in progress).
After any device reset, the Slope A/D module is disabled (lowest current state) and the device
I/O are configured as analog channels.
This module includes a high gain comparator for Slope A/D conversions. The non-inverting
input terminal of the Slope A/D comparator is connected to the output of an analog MUX through
an RC low-pass filter. The inverting input terminal is connected to the external ramp capacitor.
The output of the comparator is used to cause the capture event to occur. This causes the value
in the ADTMR registers to be loaded into the ADCAP registers. This output will also cause the
ADCIF bit to be set.
A total of 16 channels are internally multiplexed to the single Slope A/D comparator positive input.
Four configuration bits (ADCON0<7:4>) select the channel to be converted.
Four configuration bits (ADCON1<7:4>) are used to control a programmable current source for
generating the ramp voltage to the Slope A/D comparator. This allows compensation for full-scale
input voltage, clock frequency and the external capacitor tolerance variations.
Setting the ADRST bit disconnects the current source from the CDAC pin. Current flow begins
when the ADRST bit is cleared.
The programmable current source output is tied to the CDAC pin. This current source is used to
charge an external capacitor, which generates the ramp voltage for the Slope A/D comparator
(Figure
24-1).
Section 24. Slope A/D
DS31024A-page 24-9
24
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