ATMEGA168P-20PU Atmel, ATMEGA168P-20PU Datasheet - Page 213

• Manufacturer Part Number: ATMEGA168P-20PU
• Description: MCU AVR 16K FLASH 20MHZ 28-PDIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA168P-20PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Controller Family/series: AVR MEGA
• No. Of I/o's: 23
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Data Rom Size: 512 B
• A/d Bit Size: 10 bit
• A/d Channels Available: 6
• Height: 4.57 mm
• Length: 34.8 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 7.49 mm
• For Use With: ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.2.1
21.2.2
8025L–AVR–7/10
TWI Terminology
Electrical Interconnection
The following definitions are frequently encountered in this section.
Table 21-1.
The PRTWI bit in
the 2-wire Serial Interface.
As depicted in
pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector.
This implements a wired-AND function which is essential to the operation of the interface. A low
level on a TWI bus line is generated when one or more TWI devices output a zero. A high level
is output when all TWI devices tri-state their outputs, allowing the pull-up resistors to pull the line
high. Note that all AVR devices connected to the TWI bus must be powered in order to allow any
bus operation.
The number of devices that can be connected to the bus is only limited by the bus capacitance
limit of 400 pF and the 7-bit slave address space. A detailed specification of the electrical char-
acteristics of the TWI is given in
different sets of specifications are presented there, one relevant for bus speeds below 100 kHz,
and one valid for bus speeds up to 400 kHz.
Term
Master
Slave
Transmitter
Receiver
TWI Terminology
Figure
Description
The device that initiates and terminates a transmission. The Master also generates the
SCL clock.
The device addressed by a Master.
The device placing data on the bus.
The device reading data from the bus.
”Minimizing Power Consumption” on page 43
21-1, both bus lines are connected to the positive supply voltage through
”2-wire Serial Interface Characteristics” on page
ATmega48P/88P/168P
must be written to zero to enable
317. Two
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