ATMEGA168P-20PU Atmel, ATMEGA168P-20PU Datasheet - Page 303
![MCU AVR 16K FLASH 20MHZ 28-PDIP](/photos/7/21/72189/453-28-dip_sml.jpg)
ATMEGA168P-20PU
Manufacturer Part Number
ATMEGA168P-20PU
Description
MCU AVR 16K FLASH 20MHZ 28-PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA168P-20PU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Controller Family/series
AVR MEGA
No. Of I/o's
23
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
20MHz
No. Of Timers
3
Rohs Compliant
Yes
Data Rom Size
512 B
A/d Bit Size
10 bit
A/d Channels Available
6
Height
4.57 mm
Length
34.8 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
7.49 mm
For Use With
ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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27.7.12
27.7.13
8025L–AVR–7/10
Reading the Fuse and Lock Bits
Reading the Signature Bytes
1. A: Load Command “0010 0000”.
2. C: Load Data Low Byte. Bit n = “0” programs the Lock bit. If LB mode 3 is programmed
3. Give WR a negative pulse and wait for RDY/BSY to go high.
The Lock bits can only be cleared by executing Chip Erase.
The algorithm for reading the Fuse and Lock bits is as follows (refer to
on page 298
1. A: Load Command “0000 0100”.
2. Set OE to “0”, BS2 to “0” and BS1 to “0”. The status of the Fuse Low bits can now be
3. Set OE to “0”, BS2 to “1” and BS1 to “1”. The status of the Fuse High bits can now be
4. Set OE to “0”, BS2 to “1”, and BS1 to “0”. The status of the Extended Fuse bits can now
5. Set OE to “0”, BS2 to “0” and BS1 to “1”. The status of the Lock bits can now be read at
6. Set OE to “1”.
Figure 27-6. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read
The algorithm for reading the Signature bytes is as follows (refer to
page 298
1. A: Load Command “0000 1000”.
2. B: Load Address Low Byte (0x00 - 0x02).
3. Set OE to “0”, and BS1 to “0”. The selected Signature byte can now be read at DATA.
4. Set OE to “1”.
(LB1 and LB2 is programmed), it is not possible to program the Boot Lock bits by any
External Programming mode.
read at DATA (“0” means programmed).
read at DATA (“0” means programmed).
be read at DATA (“0” means programmed).
DATA (“0” means programmed).
for details on Command and Address loading):
for details on Command loading):
Extended Fuse Byte
Fuse Low Byte
Fuse High Byte
Lock Bits
BS2
BS2
0
1
0
1
ATmega48P/88P/168P
BS1
0
1
”Programming the Flash” on
”Programming the Flash”
DATA
303
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