PIC16F818-I/P Microchip Technology, PIC16F818-I/P Datasheet - Page 325

• Manufacturer Part Number: PIC16F818-I/P
• Description: IC MCU FLASH 1KX14 18-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F818-I/P

• Program Memory Type: FLASH
• Program Memory Size: 1.75KB (1K x 14)
• Package / Case: 18-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: I2C/SPI/SSP
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ACICE0202 - ADAPTER MPLABICE 18P 300 MILAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

17.4.18
1997 Microchip Technology Inc.
SDA
SCL
BCLIF
Multi -Master Communication, Bus Collision, and Bus Arbitration
Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data
bits onto the SDA pin, arbitration takes place when the master outputs a '1' on SDA by letting
SDA float high and another master asserts a '0'. When the SCL pin floats high, data should be
stable. If the expected data on SDA is a '1' and the data sampled on the SDA pin = '0', then a bus
collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLIF and reset
the I
If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF
flag is cleared, the SDA and SCL lines are de-asserted, and the SSPBUF can be written to. When
the user services the bus collision interrupt service routine, and if the I
can resume communication by asserting a START condition.
If a START, Repeated Start, STOP, or Acknowledge condition was in progress when the bus col-
lision occurred, the condition is aborted, the SDA and SCL lines are de-asserted, and the respec-
tive control bits in the SSPCON2 register are cleared. When the user services the bus collision
interrupt service routine, and if the I
ing a START condition.
The Master will continue to monitor the SDA and SCL pins, and if a STOP condition occurs, the
SSPIF bit will be set.
A write to the SSPBUF will start the transmission of data at the first data bit, regardless of where
the transmitter left off when bus collision occurred.
In multi-master mode, the interrupt generation on the detection of start and stop conditions allows
the determination of when the bus is free. Control of the I
set in the SSPSTAT register, or the bus is idle and the S and P bits are cleared.
Figure 17-34: Bus Collision Timing for Transmit and Acknowledge
2
C port to its IDLE state.
Data changes
while SCL = 0
SDA released
by master
Preliminary
(Figure
SDA line pulled low
by another source
2
C bus is free, the user can resume communication by assert-
17-34).
Section 17. MSSP
Sample SDA. While SCL is high
data doesn’t match what is driven
by the master.
Bus collision has occurred.
2
C bus can be taken when the P bit is
Set bus collision
interrupt (BCLIF).
2
C bus is free, the user
DS31017A-page 17-49
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