ATTINY28L-4AU Atmel, ATTINY28L-4AU Datasheet - Page 44

• Manufacturer Part Number: ATTINY28L-4AU
• Description: IC MCU AVR 2K FLASH 4MHZ 32-TQFP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY28L-4AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 11
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFP, 32-VQFP
• Processor Series: ATTINY2x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 32 B
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 11
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Package: 32TQFP
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 4 MHz
• Ram Size: 32 Byte
• Operating Supply Voltage: 3.3|5 V
• For Use With: ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIPATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

Analog Comparator
Register Description
Analog Comparator Control
and Status Register – ACSR
44
ATtiny28L/V
The analog comparator compares the input values on the positive input PB0 (AIN0) and
negative input PB1 (AIN1). When the voltage on the positive input PB0 (AIN0) is higher
than the voltage on the negative input PB1 (AIN1), the Analog Comparator Output
(ACO) is set (one). The comparator can trigger a separate interrupt exclusive to the ana-
log comparator. The user can select interrupt triggering on comparator output rise, fall or
toggle. A block diagram of the comparator and its surrounding logic is shown in Figure
36.
Figure 36. Analog Comparator Block Diagram
• Bit 7 – ACD: Analog Comparator Disable
When this bit is set (one), the power to the analog comparator is switched off. This bit
can be set at any time to turn off the analog comparator. When changing the ACD bit,
the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR.
Otherwise, an interrupt can occur when the bit is changed. To use the analog compara-
tor, the user must clear this bit.
• Bit 6 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny28 and will always read as zero.
• Bit 5 – ACO: Analog Comparator Output
ACO is directly connected to the comparator output.
• Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set (one) when a comparator output event triggers the interrupt mode defined
by ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE bit
is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when execut-
Bit
$08
Read/Write
Initial Value
PB0
PB1
ACD
R/W
7
1
R
6
–
0
ACO
R
X
5
R/W
ACI
4
0
ACIE
R/W
3
0
R
2
–
0
ACIS1
R/W
1
0
ACIS0
R/W
0
0
1062F–AVR–07/06
ACSR