ATA6612P-PLPW Atmel, ATA6612P-PLPW Datasheet - Page 253
![MCU W/LIN TXRX REG WTCHDG 48-QFN](/photos/6/82/68297/48-qfn_sml.jpg)
ATA6612P-PLPW
Manufacturer Part Number
ATA6612P-PLPW
Description
MCU W/LIN TXRX REG WTCHDG 48-QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet
1.ATA6612-EK.pdf
(364 pages)
Specifications of ATA6612P-PLPW
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
ATA6x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, TWI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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9111H–AUTO–01/11
To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows:
The upper 7 bits are the address to which the 2-wire Serial Interface will respond when
addressed by a Master. If the LSB is set, the TWI will respond to the general call address
(0x00), otherwise it will ignore the general call address.
TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to
enable the acknowledgement of the device’s own slave address or the general call address.
TWSTA and TWSTO must be written to zero.
When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own
slave address (or the general call address if enabled) followed by the data direction bit. If the
direction bit is “0” (write), the TWI will operate in SR mode, otherwise ST mode is entered.
After its own slave address and the write bit have been received, the TWINT Flag is set and a
valid status code can be read from TWSR. The status code is used to determine the appropri-
ate software action. The appropriate action to be taken for each status code is detailed in
Table 6-92 on page
while the TWI is in the Master mode (see states 0x68 and 0x78).
If the TWEA bit is reset during a transfer, the TWI will return a “Not Acknowledge” (“1”) to SDA
after the next received data byte. This can be used to indicate that the Slave is not able to
receive any more bytes. While TWEA is zero, the TWI does not acknowledge its own slave
address. However, the 2-wire Serial Bus is still monitored and address recognition may
resume at any time by setting TWEA. This implies that the TWEA bit may be used to tempo-
rarily isolate the TWI from the 2-wire Serial Bus.
In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA
bit is set, the interface can still acknowledge its own slave address or the general call address
by using the 2-wire Serial Bus clock as a clock source. The part will then wake up from sleep
and the TWI will hold the SCL clock low during the wake up and until the TWINT Flag is
cleared (by writing it to one). Further data reception will be carried out as normal, with the
AVR
SCL line may be held low for a long time, blocking other data transmissions.
Note that the 2-wire Serial Interface Data Register – TWDR does not reflect the last byte pres-
ent on the bus when waking up from these Sleep modes.
®
TWAR
TWCR
value
value
clocks running as normal. Observe that if the AVR is set up with a long start-up time, the
TWINT
TWA6
0
254. The Slave Receiver mode may also be entered if arbitration is lost
TWEA
TWA5
1
TWSTA
TWA4
Device’s Own Slave Address
0
Atmel ATA6612/ATA6613
TWSTO
TWA3
0
TWWC
TWA2
0
TWEN
TWA1
1
TWA0
–
0
TWGCE
TWIE
X
253
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