ATA6612P-PLPW Atmel, ATA6612P-PLPW Datasheet - Page 261
![MCU W/LIN TXRX REG WTCHDG 48-QFN](/photos/6/82/68297/48-qfn_sml.jpg)
ATA6612P-PLPW
Manufacturer Part Number
ATA6612P-PLPW
Description
MCU W/LIN TXRX REG WTCHDG 48-QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet
1.ATA6612-EK.pdf
(364 pages)
Specifications of ATA6612P-PLPW
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
ATA6x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, TWI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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9111H–AUTO–01/11
Figure 6-97. An Arbitration Example
Several different scenarios may arise during arbitration, as described below:
This is summarized in
Figure 6-98. Possible Status Codes Caused by Arbitration
START
• Two or more masters are performing identical communication with the same Slave. In this
• Two or more masters are accessing the same Slave with different data or direction bit. In
• Two or more masters are accessing different slaves. In this case, arbitration will occur in the
case, neither the Slave nor any of the masters will know about the bus contention.
this case, arbitration will occur, either in the READ/WRITE bit or in the data bits. The
masters trying to output a one on SDA while another Master outputs a zero will lose the
arbitration. Losing masters will switch to not addressed Slave mode or wait until the bus is
free and transmit a new START condition, depending on application software action.
SLA bits. Masters trying to output a one on SDA while another Master outputs a zero will
lose the arbitration. Masters losing arbitration in SLA will switch to Slave mode to check if
they are being addressed by the winning Master. If addressed, they will switch to SR or ST
mode, depending on the value of the READ/WRITE bit. If they are not being addressed,
they will switch to not addressed Slave mode or wait until the bus is free and transmit a new
START condition, depending on application software action.
SDA
SCL
Address / General Call
TRANSMITTER
Direction
received
Device 1
MASTER
Own
Yes
Arbitration lost in SLA
Figure
SLA
Write
Read
TRANSMITTER
6-98. Possible status values are given in circles.
Device 2
MASTER
No
Device 3
RECEIVER
SLAVE
68/78
38
Atmel ATA6612/ATA6613
B0
Arbitration lost in Data
TWI bus will be released and not addressed slave mode will be entered
A START condition will be transmitted when the bus becomes free
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
Last data byte will be transmitted and NOT ACK should be received
Data byte will be transmitted and ACK should be received
........
Device n
Data
V
CC
R1
R2
STOP
261
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