ATA6613P-PLQW Atmel, ATA6613P-PLQW Datasheet - Page 157

• Manufacturer Part Number: ATA6613P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6613P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: ATA6x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 6-56.
Note:
6.14.10.2
9111H–AUTO–01/11
Mode
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality and
WGM13
location of these bits are compatible with previous versions of the timer.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Timer/Counter1 Control Register B – TCCR1B
Waveform Generation Mode Bit Description
WGM12
(CTC1)
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
• Bit 7 – ICNC1: Input Capture Noise Canceler
• Bit 6 – ICES1: Input Capture Edge Select
Initial Value
Read/Write
Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise can-
celer is activated, the input from the Input Capture pin (ICP1) is filtered. The filter function
requires four successive equal valued samples of the ICP1 pin for changing its output.
The Input Capture is therefore delayed by four Oscillator cycles when the noise canceler
is enabled.
This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a cap-
ture event. When the ICES1 bit is written to zero, a falling (negative) edge is used as
trigger, and when the ICES1 bit is written to one, a rising (positive) edge will trigger the
capture.
When a capture is triggered according to the ICES1 setting, the counter value is copied
into the Input Capture Register (ICR1). The event will also set the Input Capture Flag
(ICF1), and this can be used to cause an Input Capture Interrupt, if this interrupt is
enabled.
(PWM11)
WGM11
Bit
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
ICNC1
R/W
(PWM10)
WGM10
7
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
ICES1
R/W
6
0
Timer/Counter Mode of
Operation
Normal
PWM, Phase Correct, 8-bit
PWM, Phase Correct, 9-bit
PWM, Phase Correct, 10-bit
CTC
Fast PWM, 8-bit
Fast PWM, 9-bit
Fast PWM, 10-bit
PWM, Phase and Frequency
Correct
PWM, Phase and Frequency
Correct
PWM, Phase Correct
PWM, Phase Correct
CTC
(Reserved)
Fast PWM
Fast PWM
(1)
R
5
–
0
WGM13
R/W
4
0
Atmel ATA6612/ATA6613
WGM12
R/W
3
0
TOP
0xFFFF
0x00FF
0x01FF
0x03FF
OCR1A
0x00FF
0x01FF
0x03FF
ICR1
OCR1A
ICR1
OCR1A
ICR1
–
ICR1
OCR1A
CS12
R/W
2
0
Update of
OCR1
Immediate
TOP
Immediate
TOP
TOP
TOP
BOTTOM
BOTTOM
TOP
Immediate
–
TOP
TOP
TOP
TOP
TOP
CS11
R/W
1
0
x
at
CS10
R/W
0
0
TOV1 Flag
Set on
MAX
BOTTOM
BOTTOM
BOTTOM
MAX
TOP
TOP
TOP
BOTTOM
BOTTOM
BOTTOM
BOTTOM
MAX
–
TOP
TOP
TCCR1B
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