PIC18F25K22-I/SP Microchip Technology, PIC18F25K22-I/SP Datasheet - Page 328
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PIC18F25K22-I/SP
Manufacturer Part Number
PIC18F25K22-I/SP
Description
MCU 8BIT 32KB FLASH 5.5V 28SDIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC18F26J13-ISS.pdf
(496 pages)
3.PIC18F25K22T-ISS.pdf
(10 pages)
4.PIC18F25K22-ISP.pdf
(492 pages)
Specifications of PIC18F25K22-I/SP
Program Memory Type
FLASH
Program Memory Size
32KB (16K x 16)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 19x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1536 B
Interface Type
I2C, SPI, EUSART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
25
Number Of Timers
7
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 17 Channel
On-chip Dac
5 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F25K22-I/SP
Manufacturer:
MICROCHIP
Quantity:
1 200
- PIC16F722-ISS PDF datasheet
- PIC18F26J13-ISS PDF datasheet #2
- PIC18F25K22T-ISS PDF datasheet #3
- PIC18F25K22-ISP PDF datasheet #4
- Current page: 328 of 492
- Download datasheet (5Mb)
PIC18(L)F2X/4XK22
19.6
A unique feature on board the CTMU module is its
ability to generate system clock independent output
pulses based on an external capacitor value. This is
accomplished using the internal comparator voltage
reference module, Comparator 2 input pin and an
external capacitor. The pulse is output onto the CTPLS
pin. To enable this mode, set the TGEN bit.
See Figure 19-4 for an example circuit. C
chosen by the user to determine the output pulse width
on CTPLS. The pulse width is calculated by
T = (C
source measurement step (Section 19.3.1 “Current
Source Calibration”) and V is the internal reference
voltage (CV
FIGURE 19-4:
19.7
19.7.1
When the device enters any Sleep mode, the CTMU
module current source is always disabled. If the CTMU
is performing an operation that depends on the current
source when Sleep mode is invoked, the operation may
not
measurements may return erroneous values.
19.7.2
The behavior of the CTMU in Idle mode is determined
by the CTMUSIDL bit (CTMUCONH<5>). If CTMUSIDL
is cleared, the module will continue to operate in Idle
mode. If CTMUSIDL is set, the module’s current source
is disabled when the device enters Idle mode. If the
DS41412B-page 328
terminate
PULSE
Creating a Delay with the CTMU
Module
Operation During Sleep/Idle
Modes
/I)*V, where I is known from the current
REF
SLEEP MODE AND DEEP SLEEP
MODES
IDLE MODE
).
correctly.
TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE
DELAY GENERATION
C12IN1-
C
CTED1
PULSE
Capacitance
and
PULSE
PIC18(L)FXXK22 Device
EDG1
time
Preliminary
CV
is
Current Source
REF
Comparator
CTMU
C2
An example use of this feature is for interfacing with
variable capacitive-based sensors, such as a humidity
sensor. As the humidity varies, the pulse width output
on CTPLS will vary. The CTPLS output pin can be con-
nected to an input capture pin and the varying pulse
width is measured to determine the humidity in the
application.
Follow these steps to use this feature:
1.
2.
3.
4.
5.
module is performing an operation when Idle mode is
invoked, in this case, the results will be similar to those
with Sleep mode.
19.8
When this peripheral is not used, the Peripheral
Module Disable bit can be set to disconnect all clock
sources to the module, reducing power consumption to
an absolute minimum. See Section 3.6 “Selective
Peripheral Module Control”.
Initialize Comparator 2.
Initialize the comparator voltage reference.
Initialize the CTMU and enable time delay
generation by setting the TGEN bit.
Set EDG1STAT.
When C
reference trip point, an output pulse is generated
on CTPLS.
CTMU Peripheral Module Disable
(PMD)
PULSE
charges to the value of the voltage
CTPLS
2010 Microchip Technology Inc.
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