PIC18F25K22-I/SP Microchip Technology, PIC18F25K22-I/SP Datasheet - Page 486

• Manufacturer Part Number: PIC18F25K22-I/SP
• Description: MCU 8BIT 32KB FLASH 5.5V 28SDIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F25K22-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 19x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1536 B
• Interface Type: I2C, SPI, EUSART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 7
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 17 Channel
• On-chip Dac: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18(L)F2X/4XK22
Timer2
Timer2/4/6 ........................................................................ 173
Timers
Timing Diagrams
DS41412B-page 486
Asynchronous Counter Mode .................................. 163
Clock Source Selection ............................................ 162
Interrupt .................................................................... 166
Operation ................................................................. 162
Operation During Sleep ........................................... 166
Oscillator .................................................................. 163
Prescaler .................................................................. 163
Timer1 Gate
TMR1H Register ...................................................... 161
TMR1L Register ....................................................... 161
Associated registers ................................................. 176
Associated registers ................................................. 176
Timer1
Timer2/4/6
A/D Conversion ........................................................ 459
Acknowledge Sequence .......................................... 246
Asynchronous Reception ......................................... 271
Asynchronous Transmission .................................... 266
Asynchronous Transmission (Back to Back) ........... 267
Auto Wake-up Bit (WUE) During Normal
Auto Wake-up Bit (WUE) During Sleep ................... 281
Automatic Baud Rate Calculator .............................. 280
Baud Rate Generator with Clock Arbitration ............ 239
BRG Reset Due to SDA Arbitration During Start
Brown-out Reset (BOR) ........................................... 446
Bus Collision During a Repeated Start Condition
Bus Collision During a Repeated Start Condition
Bus Collision During a Start Condition (SCL = 0) .... 250
Bus Collision During a Stop Condition (Case 1) ...... 252
Bus Collision During a Stop Condition (Case 2) ...... 252
Bus Collision During Start Condition (SDA only) ..... 249
Bus Collision for Transmit and Acknowledge ........... 248
Capture/Compare/PWM (CCP) ................................ 448
CLKO and I/O .......................................................... 445
Clock Synchronization ............................................. 236
Clock/Instruction Cycle .............................................. 74
Comparator Output .................................................. 305
EUSART Synchronous Receive (Master/Slave) ...... 458
EUSART Synchronous Transmission
Example SPI Master Mode (CKE = 0) ..................... 449
Example SPI Master Mode (CKE = 1) ..................... 450
Example SPI Master Mode Timing .......................... 449
Example SPI Slave Mode (CKE = 0) ....................... 451
Example SPI Slave Mode (CKE = 1) ....................... 452
External Clock (All Modes except PLL) .................... 443
Fail-Safe Clock Monitor (FSCM) ................................ 45
First Start Bit Timing ................................................ 240
Full-Bridge PWM Output .......................................... 193
Half-Bridge PWM Output ................................. 191, 197
High/Low-Voltage Detect Characteristics ................ 440
High-Voltage Detect Operation (VDIRMAG = 1) ...... 346
Reading and Writing ........................................ 163
Selecting Source .............................................. 164
T1CON ............................................................. 170
T1GCON .......................................................... 171
TXCON ............................................................ 175
Operation ......................................................... 281
Condition .......................................................... 250
(Case 1) ........................................................... 251
(Case 2) ........................................................... 251
(Master/Slave) .................................................. 458
Preliminary
Timing Diagrams and Specifications ............................... 443
I
I
I
I
I
Internal Oscillator Switch Timing ............................... 43
Low-Voltage Detect Operation (VDIRMAG = 0) ...... 345
Master SSP I
Master SSP I
PWM Auto-shutdown ............................................... 196
PWM Direction Change ........................................... 194
PWM Direction Change at Near 100% Duty Cycle .. 195
PWM Output (Active-High) ...................................... 189
PWM Output (Active-Low) ....................................... 190
Repeat Start Condition ............................................ 241
Reset, Watchdog Timer (WDT), Oscillator Start-up
Send Break Character Sequence ............................ 282
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ......................................... 213
Synchronous Reception (Master Mode, SREN) ...... 287
Synchronous Transmission ..................................... 284
Synchronous Transmission (Through TXEN) .......... 284
Time-out Sequence on POR w/PLL Enabled
Time-out Sequence on Power-up (MCLR Not
Time-out Sequence on Power-up (MCLR Not
Time-out Sequence on Power-up (MCLR Tied
Timer0 and Timer1 External Clock .......................... 447
Timer1 Incrementing Edge ...................................... 167
Transition for Entry to SEC_RUN Mode .................... 49
Transition for Entry to Sleep Mode ............................ 51
Transition for Wake from Sleep (HSPLL) .................. 52
Transition from RC_RUN Mode to PRI_RUN Mode .. 50
Transition from SEC_RUN Mode to PRI_RUN
Transition Timing for Entry to Idle Mode .................... 52
Transition Timing for Wake from Idle to Run Mode ... 53
A/D Conversion Requirements ................................ 460
Capture/Compare/PWM Requirements ................... 449
CLKO and I/O Requirements ................................... 445
EUSART Synchronous Receive Requirements ....... 458
EUSART Synchronous Transmission
Example SPI Mode Requirements
External Clock Requirements .................................. 443
I
I
Master SSP I
Master SSP I
PLL Clock ................................................................ 444
2
2
2
2
2
2
2
C Bus Data ............................................................ 454
C Bus Start/Stop Bits ............................................ 453
C Master Mode (7 or 10-Bit Transmission) ........... 243
C Master Mode (7-Bit Reception) .......................... 245
C Stop Condition Receive or Transmit Mode ........ 247
C Bus Data Requirements (Slave Mode) .............. 455
C Bus Start/Stop Bits Requirements
Firmware Restart ............................................. 196
Timer (OST), Power-up Timer (PWRT) ........... 446
T
(MCLR Tied to V
Tied to V
Tied to V
to V
Mode (HSPLL) ................................................... 49
Requirements .................................................. 458
(Master Mode, CKE = 0) .................................. 450
(Master Mode, CKE = 1) .................................. 451
(Slave Mode, CKE = 0) .................................... 452
(Slave Mode, CKE = 1) .................................... 453
(Slave Mode) ................................................... 454
Requirements .................................................. 456
PWRT
DD
) ............................................................... 65
, V
2
2
2
2
DD
DD
C Bus Data ........................................ 456
C Bus Start/Stop Bits ........................ 456
C Bus Data Requirements ................ 457
C Bus Start/Stop Bits
DD
, Case 1) ......................................... 64
, Case 2) ......................................... 65
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DD
) .......................................... 66
PWRT
) ............................... 64
DD
, V
DD
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