PIC18F25K22-I/SP Microchip Technology, PIC18F25K22-I/SP Datasheet - Page 451

• Manufacturer Part Number: PIC18F25K22-I/SP
• Description: MCU 8BIT 32KB FLASH 5.5V 28SDIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F25K22-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 19x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1536 B
• Interface Type: I2C, SPI, EUSART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 7
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 17 Channel
• On-chip Dac: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TABLE 27-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
FIGURE 27-12:
 2010 Microchip Technology Inc.
Param.
71
71A
72
72A
73
73A
74
75
76
78
79
80
81
Note 1:
No.
(CKP = 0)
(CKP = 1)
SDI
SDI
SS
SCK
SCK
SDO
Note:
2:
TscH
TscL
TdiV2scH,
TdiV2scL
Tb2b
TscH2diL,
TscL2diL
TdoR
TdoF
TscR
TscF
TscH2doV,
TscL2doV
TdoV2scH,
TdoV2scL
Symbol
Requires the use of Parameter #73A.
Only if Parameter #71A and #72A are used.
Refer to Figure 27-3 for load conditions.
EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SCK Input High Time
(Slave mode)
SCK Input Low Time
(Slave mode)
Setup Time of SDI Data Input to SCK Edge
Last Clock Edge of Byte 1 to the 1st Clock Edge
of Byte 2
Hold Time of SDI Data Input to SCK Edge
SDO Data Output Rise Time
SDO Data Output Fall Time
SCK Output Rise Time
(Master mode)
SCK Output Fall Time (Master mode)
SDO Data Output Valid after SCK Edge
SDO Data Output Setup to SCK Edge
70
80
71
73
MSb In
Characteristic
MSb
74
72
75, 76
Preliminary
Continuous
Single Byte
Continuous
Single Byte
bit 6 - - - - - -1
bit 6 - - - -1
PIC18(L)F2X/4XK22
78
79
1.25 T
1.25 T
1.5 T
Min
100
100
T
CY
40
40
—
—
—
—
—
79
78
CY
CY
CY
LSb In
+ 40
LSb
+ 30
+ 30
83
Max Units
25
25
25
25
50
—
—
—
—
—
—
—
—
77
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS41412B-page 451
(Note 1)
(Note 1)
(Note 2)
Conditions