PIC18F47J53T-I/ML Microchip Technology, PIC18F47J53T-I/ML Datasheet - Page 549

IC MCU 8BIT 128KB FLASH 44 QFN

PIC18F47J53T-I/ML

Manufacturer Part Number
PIC18F47J53T-I/ML
Description
IC MCU 8BIT 128KB FLASH 44 QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets

Specifications of PIC18F47J53T-I/ML

Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
*
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
34
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 13x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.8 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
22
Number Of Timers
8
Operating Supply Voltage
2.15 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA180029 - BOARD DEMO PIC18F47J53 FS USB
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F47J53T-I/ML
Manufacturer:
MURATA
Quantity:
640 000
TABLE 31-27: MSSPx I
 2010 Microchip Technology Inc.
100
101
102
103
90
91
106
107
92
109
110
D102
Legend: TBD = To Be Determined
Note 1:
Param.
No.
2:
T
T
T
T
T
T
T
T
T
T
T
C
Symbol
SU
SU
SU
AA
R
HIGH
LOW
F
HD
HD
BUF
B
Maximum pin capacitance = 10 pF for all I
A Fast mode I
#107  250 ns must then be met. This will automatically be the case if the device does not stretch the LOW
period of the SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output
the next data bit to the SDAx line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz
mode), before the SCLx line is released.
:
:
:
:
:
STA
DAT
STO
STA
DAT
Clock High Time 100 kHz mode
Clock Low Time 100 kHz mode
SDAx and SCLx
Rise Time
SDAx and SCLx
Fall Time
Start Condition
Setup Time
Start Condition
Hold Time
Data Input
Hold Time
Data Input
Setup Time
Stop Condition
Setup Time
Output Valid
from Clock
Bus Free Time
Bus Capacitive Loading
2
C bus device can be used in a Standard mode I
2
C™ BUS DATA REQUIREMENTS
Characteristic
400 kHz mode
1 MHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Preliminary
2
C™ pins.
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
OSC
OSC
OSC
OSC
OSC
OSC
20 + 0.1 C
20 + 0.1 C
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
PIC18F47J53 FAMILY
TBD
TBD
TBD
Min
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
250
100
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
4.7
1.3
0
0
B
B
2
C bus system, but parameter
1000
3500
1000
Max
300
300
300
300
100
0.9
400
Units
pF
s
s
s
s
s
s
ns
ns
ns
ns
ns
ns
s
s
s
s
s
s
ns
s
ns
ns
ns
ns
s
s
s
ns
ns
ns
s
s
s
C
from 10 to 400 pF
C
from 10 to 400 pF
Only relevant for
Repeated Start condition
After this period, the first
clock pulse is generated
(Note 2)
Time the bus must be
free before a new
transmission can start
B
B
is specified to be
is specified to be
Conditions
DS39964B-page 549

Related parts for PIC18F47J53T-I/ML