PIC18F1220-I/SS Microchip Technology, PIC18F1220-I/SS Datasheet - Page 131

• Manufacturer Part Number: PIC18F1220-I/SS
• Description: IC MCU FLASH 2KX16 A/D 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F1220-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 4KB (2K x 16)
• Package / Case: 20-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 7-ch x 10-bit
• Package: 20SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164307 - MODULE SKT FOR PM3 28SSOPAC164018 - MODULE SKT PROMATEII 20SSOP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.5.9
The following steps should be taken when configuring
the ECCP1 module for PWM operation:
1.
2.
3.
4.
5.
6.
7.
8.
9.
 2004 Microchip Technology Inc.
Configure the PWM pins P1A and P1B (and
P1C and P1D, if used) as inputs by setting the
corresponding TRISB bits.
Set the PWM period by loading the PR2 register.
Configure the ECCP module for the desired
PWM mode and configuration by loading the
CCP1CON register with the appropriate values:
• Select one of the available output
• Select the polarities of the PWM output
Set the PWM duty cycle by loading the CCPR1L
register and CCP1CON<5:4> bits.
For Half-Bridge Output mode, set the dead-
band delay by loading PWM1CON<6:0> with
the appropriate value.
If auto-shutdown operation is required, load the
ECCPAS register:
• Select the auto-shutdown sources using the
• Select the shutdown states of the PWM
• Set the ECCPASE bit (ECCPAS<7>).
If auto-restart operation is required, set the
PRSEN bit (PWM1CON<7>).
Configure and start TMR2:
• Clear the TMR2 interrupt flag bit by clearing
• Set the TMR2 prescale value by loading the
• Enable Timer2 by setting the TMR2ON bit
Enable PWM outputs after a new PWM cycle
has started:
• Wait until TMR2 overflows (TMR2IF bit is set).
• Enable the CCP1/P1A, P1B, P1C and/or P1D
• Clear the ECCPASE bit (ECCPAS<7>).
configurations and direction with the
P1M1:P1M0 bits.
signals with the CCP1M3:CCP1M0 bits.
ECCPAS<2:0> bits.
output pins using PSSAC1:PSSAC0 and
PSSBD1:PSSBD0 bits.
the TMR2IF bit (PIR1<1>).
T2CKPS bits (T2CON<1:0>).
(T2CON<2>).
pin outputs by clearing the respective TRISB
bits.
SETUP FOR PWM OPERATION
15.5.10
In the Low-Power Sleep mode, all clock sources are
disabled. Timer2 will not increment and the state of the
module will not change. If the ECCP pin is driving a
value, it will continue to drive that value. When the
device wakes up, it will continue from this state. If Two-
Speed Start-ups are enabled, the initial start-up
frequency may not be stable if the INTOSC is being
used.
In PRI_IDLE mode, the primary clock will continue to
clock the ECCP module without change.
In all other low-power modes, the selected low-power
mode clock will clock Timer2. Other low-power mode
clocks will most likely be different than the primary
clock frequency.
15.5.10.1
If
(CONFIG1H<6> is programmed), a clock failure will
force the device into the Low-Power RC_RUN mode
and the OSCFIF bit (PIR2<7>) will be set. The ECCP
will then be clocked from the INTRC clock source,
which may have a different clock frequency than the
primary clock. By loading the IRCF2:IRCF0 bits on
Resets, the user can enable the INTOSC at a high
clock speed in the event of a clock failure.
See the previous section for additional details.
15.5.11
Both power-on and subsequent Resets will force all
ports to input mode and the CCP registers to their
Reset states.
This forces the Enhanced CCP module to reset to a
state compatible with the standard CCP module.
the
PIC18F1220/1320
Fail-Safe
OPERATION IN LOW-POWER
MODES
EFFECTS OF A RESET
Operation with Fail-Safe
Clock Monitor
Clock
Monitor
DS39605C-page 129
is
enabled