PIC18F1220-I/SS Microchip Technology, PIC18F1220-I/SS Datasheet - Page 225

• Manufacturer Part Number: PIC18F1220-I/SS
• Description: IC MCU FLASH 2KX16 A/D 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F1220-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 4KB (2K x 16)
• Package / Case: 20-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 7-ch x 10-bit
• Package: 20SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164307 - MODULE SKT FOR PM3 28SSOPAC164018 - MODULE SKT PROMATEII 20SSOP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

RETURN
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
 2004 Microchip Technology Inc.
Q Cycle Activity:
After Interrupt
operation
Decode
PC =
Q1
No
TOS
operation
operation
Return from Subroutine
[ label ]
s
(TOS)
if s = 1
(WS)
(STATUSS)
(BSRS)
PCLATU, PCLATH are unchanged
None
Return from subroutine. The stack
is popped and the top of the stack
is loaded into the program counter.
If ‘s’= 1, the contents of the shadow
registers, WS, STATUSS and
BSRS, are loaded into their corre-
sponding registers, W, Status and
BSR. If ‘s’ = 0, no update of these
registers occurs (default).
1
2
RETURN
0000
Q2
No
No
[0,1]
W,
PC,
RETURN [s]
BSR,
0000
operation
Process
Data
Status,
Q3
No
0001
from stack
operation
Pop PC
Q4
No
001s
RLCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
C
REG
W
C
Q1
PIC18F1220/1320
=
=
=
=
=
register ‘f’
Rotate Left f through Carry
[ label ]
0
d
a
(f<n>)
(f<7>)
(C)
C, N, Z
The contents of register ‘f’ are
rotated one bit to the left through
the Carry flag. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is stored back in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
1
1
RLCF
Read
Q2
0011
1110 0110
0
1110 0110
1100 1100
1
f
[0,1]
[0,1]
C
dest<0>
255
dest<n + 1>,
C,
RLCF
01da
Process
Data
Q3
REG, W
register f
DS39605C-page 223
f [,d [,a]]
ffff
destination
Write to
Q4
ffff