PIC18LF2221-I/SS Microchip Technology, PIC18LF2221-I/SS Datasheet - Page 121
![IC PIC MCU FLASH 2KX16 28SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC18LF2221-I/SS
Manufacturer Part Number
PIC18LF2221-I/SS
Description
IC PIC MCU FLASH 2KX16 28SSOP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(402 pages)
2.PIC18F2221-ISO.pdf
(8 pages)
3.PIC18F2221-ISO.pdf
(30 pages)
4.PIC18F2221-ISO.pdf
(46 pages)
5.PIC18LF2221-IML.pdf
(394 pages)
Specifications of PIC18LF2221-I/SS
Core Size
8-Bit
Program Memory Size
4KB (2K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF2221-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC18F2221-ISO PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2221-ISO PDF datasheet #3
- PIC18F2221-ISO PDF datasheet #4
- PIC18LF2221-IML PDF datasheet #5
- Current page: 121 of 394
- Download datasheet (7Mb)
TABLE 10-9:
TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
© 2005 Microchip Technology Inc.
PORTE
LATE
TRISE
ADCON1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Note 1:
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
MCLR/V
Legend:
Note 1:
Name
(2)
2:
2:
Pin
PP
/RE3
Implemented only when Master Clear functionality is disabled (MCLRE configuration bit = 0).
RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are
implemented only when PORTE is implemented (i.e., 40/44-pin devices).
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
RE3 is available on both 28-pin and 40/44-pin devices. All other PORTE pins are only implemented on 40/44-pin devices.
RE3 does not have a corresponding TRIS bit to control data direction.
(1)
Bit 7
IBF
—
—
—
PORTE I/O SUMMARY
Function
MCLR
RE0
AN5
RE1
AN6
RE2
AN7
RE3
WR
V
RD
CS
PP
Bit 6
OBF
—
—
—
Setting
TRIS
—
—
—
0
1
1
1
0
1
1
1
0
1
1
1
(2)
VCFG1
IBOV
Bit 5
I/O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
—
—
Advance Information
Type
ANA
ANA
ANA
ANA
DIG
TTL
DIG
TTL
DIG
TTL
I/O
ST
ST
ST
ST
ST
PSPMODE
VCFG0
Bit 4
—
—
LATE<0> data output; not affected by analog input.
PORTE<0> data input; disabled when analog input enabled.
PSP read enable input (PSP enabled).
A/D input channel 5; default input configuration on POR.
LATE<1> data output; not affected by analog input.
PORTE<1> data input; disabled when analog input enabled.
PSP write enable input (PSP enabled).
A/D input channel 6; default input configuration on POR.
LATE<2> data output; not affected by analog input.
PORTE<2> data input; disabled when analog input enabled.
PSP write enable input (PSP enabled).
A/D input channel 7; default input configuration on POR.
External Master Clear input; enabled when MCLRE configuration bit
is set.
High-voltage detection; used for ICSP™ mode entry detection. Always
available, regardless of pin mode.
PORTE<3> data input; enabled when MCLRE configuration bit is clear.
RE3
PCFG3
Bit 3
PIC18F4321 FAMILY
—
—
(1,2)
PORTE Data Latch Register
(Read and Write to Data Latch)
TRISE2
PCFG2
Bit 2
RE2
Description
TRISE1
PCFG1
Bit 1
RE1
TRISE0
PCFG0
Bit 0
DS39689A-page 119
RE0
on page
Values
Reset
52
51
52
52
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