PIC18LF2221-I/SS Microchip Technology, PIC18LF2221-I/SS Datasheet - Page 389

• Manufacturer Part Number: PIC18LF2221-I/SS
• Description: IC PIC MCU FLASH 2KX16 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF2221-I/SS

• Core Size: 8-Bit
• Program Memory Size: 4KB (2K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

© 2005 Microchip Technology Inc.
Bus Collision During a Repeated Start
Bus Collision During a Repeated Start
Bus Collision During a Start Condition
Bus Collision During a Stop Condition
Bus Collision During a Stop Condition
Bus Collision During Start Condition
Bus Collision for Transmit and Acknowledge ........... 199
Capture/Compare/PWM (All CCP Modules) ............ 352
CLKO and I/O .......................................................... 349
Clock Synchronization ............................................. 185
Clock/Instruction Cycle .............................................. 57
EUSART Synchronous Receive
EUSART Synchronous Transmission
Example SPI Master Mode (CKE = 0) ..................... 354
Example SPI Master Mode (CKE = 1) ..................... 355
Example SPI Slave Mode (CKE = 0) ....................... 356
Example SPI Slave Mode (CKE = 1) ....................... 357
External Clock (All Modes Except PLL) ................... 347
Fail-Safe Clock Monitor ............................................ 267
First Start Bit Timing ................................................ 193
Full-Bridge PWM Output .......................................... 153
Half-Bridge PWM Output ......................................... 152
High/Low-Voltage Detect Characteristics ................ 344
High-Voltage Detect Operation
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Low-Voltage Detect Operation
Master SSP I
Master SSP I
Parallel Slave Port (PIC18F4221/4321) ................... 353
Parallel Slave Port (PSP) Read ............................... 121
Parallel Slave Port (PSP) Write ............................... 121
PWM Auto-Shutdown (PRSEN = 0,
PWM Auto-Shutdown (PRSEN = 1,
PWM Direction Change ........................................... 155
PWM Direction Change at Near
PWM Output ............................................................ 144
2
2
2
2
2
2
2
2
2
2
2
2
2
2
C Bus Data ............................................................ 358
C Bus Start/Stop Bits ............................................. 358
C Master Mode (7 or 10-Bit Transmission) ........... 196
C Master Mode (7-Bit Reception) .......................... 197
C Slave Mode (10-Bit Reception, SEN = 0) .......... 182
C Slave Mode (10-Bit Reception, SEN = 0,
C Slave Mode (10-Bit Reception, SEN = 1) .......... 187
C Slave Mode (10-Bit Transmission) ..................... 183
C Slave Mode (7-Bit Reception, SEN = 0) ............ 178
C Slave Mode (7-bit Reception, SEN = 0,
C Slave Mode (7-Bit Reception, SEN = 1) ............ 186
C Slave Mode (7-Bit Transmission) ....................... 180
C Slave Mode General Call Address
C Stop Condition Receive or Transmit Mode ........ 198
Condition (Case 1) ........................................... 202
Condition (Case 2) ........................................... 202
(SCL = 0) ......................................................... 201
(Case 1) ........................................................... 203
(Case 2) ........................................................... 203
(SDA Only) ....................................................... 200
(Master/Slave) ................................................. 362
(Master/Slave) ................................................. 362
(VDIRMAG = 1) ................................................ 250
ADMSK = 01001) ............................................. 181
ADMSK = 01011) ............................................. 179
Sequence (7 or 10-Bit Address Mode) ............ 188
(VDIRMAG = 0) ................................................ 249
Auto-Restart Disabled) .................................... 158
Auto-Restart Enabled) ..................................... 158
100% Duty Cycle ............................................. 155
2
2
C Bus Data ........................................ 360
C Bus Start/Stop Bits ........................ 360
Advance Information
Timing Diagrams and Specifications ............................... 347
Top-of-Stack Access .......................................................... 54
PIC18F4321 FAMILY
Repeat Start Condition ............................................ 194
Reset, Watchdog Timer (WDT), Oscillator Start-up
Send Break Character Sequence ............................ 221
Slave Synchronization ............................................. 167
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ........................................ 166
SPI Mode (Slave Mode, CKE = 0) ........................... 168
SPI Mode (Slave Mode, CKE = 1) ........................... 168
Synchronous Reception
Synchronous Transmission ..................................... 222
Synchronous Transmission (Through TXEN) .......... 223
Time-out Sequence on POR w/PLL Enabled
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock .......................... 351
Transition for Entry to Idle Mode ............................... 38
Transition for Entry to SEC_RUN Mode .................... 35
Transition for Entry to Sleep Mode ............................ 37
Transition for Two-Speed Start-up
Transition for Wake from Idle to Run Mode ............... 38
Transition for Wake from Sleep (HSPLL) .................. 37
Transition from RC_RUN Mode to
Transition from SEC_RUN Mode to
Transition to RC_RUN Mode ..................................... 36
Capture/Compare/PWM Requirements
CLKO and I/O Requirements ................................... 349
EUSART Synchronous Receive Requirements ....... 362
EUSART Synchronous Transmission
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
External Clock Requirements .................................. 347
I
Master SSP I
Master SSP I
Parallel Slave Port Requirements
PLL Clock ................................................................ 348
Reset, Watchdog Timer, Oscillator Start-up
Timer0 and Timer1 External
2
C Bus Data Requirements (Slave Mode) .............. 359
Timer (OST), Power-up Timer (PWRT) ........... 350
V
(Master Mode, SREN) ..................................... 224
(MCLR Tied to V
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
(INTOSC to HSPLL) ........................................ 265
PRI_RUN Mode ................................................. 36
PRI_RUN Mode (HSPLL) .................................. 35
(All CCP Modules) ........................................... 352
Requirements .................................................. 362
(Master Mode, CKE = 0) .................................. 354
(Master Mode, CKE = 1) .................................. 355
(Slave Mode, CKE = 0) .................................... 356
(Slave Mode, CKE = 1) .................................... 357
Requirements .................................................. 360
(PIC18F4221/4321) ......................................... 353
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 350
Clock Requirements ........................................ 351
DD
Rise > T
2
2
C Bus Data Requirements ................ 361
C Bus Start/Stop Bits
PWRT
DD
DD
) ............................................ 47
) .......................................... 47
, V
DD
DD
DD
, Case 1) ...................... 46
, Case 2) ...................... 46
Rise < T
DD
DS39689A-page 387
,
PWRT
) ........... 46