PIC18LF2221-I/SS Microchip Technology, PIC18LF2221-I/SS Datasheet - Page 383
![IC PIC MCU FLASH 2KX16 28SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC18LF2221-I/SS
Manufacturer Part Number
PIC18LF2221-I/SS
Description
IC PIC MCU FLASH 2KX16 28SSOP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(402 pages)
2.PIC18F2221-ISO.pdf
(8 pages)
3.PIC18F2221-ISO.pdf
(30 pages)
4.PIC18F2221-ISO.pdf
(46 pages)
5.PIC18LF2221-IML.pdf
(394 pages)
Specifications of PIC18LF2221-I/SS
Core Size
8-Bit
Program Memory Size
4KB (2K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF2221-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC18F2221-ISO PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2221-ISO PDF datasheet #3
- PIC18F2221-ISO PDF datasheet #4
- PIC18LF2221-IML PDF datasheet #5
- Current page: 383 of 394
- Download datasheet (7Mb)
Data Memory ..................................................................... 59
DAW ................................................................................. 292
DC and AC Characteristics
DC Characteristics ........................................................... 340
DCFSNZ .......................................................................... 293
DECF ............................................................................... 292
DECFSZ ........................................................................... 293
Dedicated ICD/ICSP Port ................................................. 271
Development Support ...................................................... 323
Device Differences ........................................................... 375
Device Overview .................................................................. 7
Device Reset Timers .......................................................... 45
Direct Addressing ............................................................... 68
E
Effect on Standard PIC Instructions ................................. 320
Effects of Power-Managed Modes on
Electrical Characteristics .................................................. 327
Enhanced Capture/Compare/PWM (ECCP) .................... 147
Enhanced PWM Mode. See PWM (ECCP Module).
Enhanced Universal Synchronous Asynchronous
Equations
Errata ................................................................................... 6
EUSART
© 2005 Microchip Technology Inc.
Write Verify ................................................................ 85
Writing ........................................................................ 85
Access Bank .............................................................. 61
and the Extended Instruction Set ............................... 69
Bank Select Register (BSR) ....................................... 59
General Purpose Registers ........................................ 61
Map for PIC18F4321 Family ...................................... 60
Special Function Registers ........................................ 62
Graphs and Tables .................................................. 365
Power-Down and Supply Current ............................ 331
Supply Voltage ......................................................... 330
Details on Individual Family Members ......................... 8
Features (table) ............................................................ 9
New Core Features ...................................................... 7
Other Special Features ................................................ 8
Oscillator Start-up Timer (OST) ................................. 45
PLL Lock Time-out ..................................................... 45
Power-up Timer (PWRT) ........................................... 45
Time-out Sequence .................................................... 45
Various Clock Sources ............................................... 32
Associated Registers ............................................... 160
Capture and Compare Modes .................................. 148
Capture Mode. See Capture (ECCP Module).
Outputs and Configuration ....................................... 148
Pin Configurations for ECCP1 ................................. 148
PWM Mode. See PWM (ECCP Module).
Standard PWM Mode ............................................... 148
Timer Resources ...................................................... 148
Receiver Transmitter (EUSART). See EUSART.
A/D Acquisition Time ................................................ 232
A/D Minimum Charging Time ................................... 232
Asynchronous Mode ................................................ 215
12-Bit Break Transmit and Receive ................. 221
Associated Registers, Receive ........................ 219
Associated Registers, Transmit ....................... 217
Auto-Wake-up on Sync Break ......................... 220
Receiver ........................................................... 218
Setting up 9-Bit Mode with
Transmitter ....................................................... 215
Address Detect ........................................ 218
Advance Information
Extended Instruction Set
External Clock Input ........................................................... 24
F
Fail-Safe Clock Monitor ........................................... 253, 266
Fast Register Stack ........................................................... 56
Firmware Instructions ...................................................... 273
Flash Program Memory ..................................................... 73
FSCM. See Fail-Safe Clock Monitor.
PIC18F4321 FAMILY
Baud Rate Generator
Baud Rate Generator (BRG) ................................... 209
Synchronous Master Mode ...................................... 222
Synchronous Slave Mode ........................................ 225
ADDFSR .................................................................. 316
ADDULNK ............................................................... 316
and Using MPLAB IDE Tools .................................. 322
CALLW .................................................................... 317
Considerations for Use ............................................ 320
MOVSF .................................................................... 317
MOVSS .................................................................... 318
PUSHL ..................................................................... 318
SUBFSR .................................................................. 319
SUBULNK ................................................................ 319
Syntax ...................................................................... 315
Exiting Operation ..................................................... 266
Interrupts in Power-Managed Modes ...................... 267
POR or Wake from Sleep ........................................ 267
WDT During Oscillator Failure ................................. 266
Associated Registers ................................................. 81
Control Registers ....................................................... 74
Erase Sequence ........................................................ 78
Erasing ...................................................................... 78
Operation During Code-Protect ................................. 81
Reading ..................................................................... 77
Table Pointer
Table Reads and Table Writes .................................. 73
Write Sequence ......................................................... 79
Writing ....................................................................... 79
Operation in Power-Managed Mode ................ 209
Associated Registers ....................................... 210
Auto-Baud Rate Detect .................................... 213
Baud Rate Error, Calculating ........................... 210
Baud Rates, Asynchronous Modes ................. 211
High Baud Rate Select (BRGH Bit) ................. 209
Sampling ......................................................... 209
Associated Registers, Receive ........................ 224
Associated Registers, Transmit ....................... 223
Reception ........................................................ 224
Transmission ................................................... 222
Associated Registers, Receive ........................ 226
Associated Registers, Transmit ....................... 225
Reception ........................................................ 226
Transmission ................................................... 225
EECON1 and EECON2 ..................................... 74
TABLAT (Table Latch) Register ........................ 76
TBLPTR (Table Pointer) Register ...................... 76
Boundaries ........................................................ 76
Boundaries Based on Operation ....................... 76
Operations with TBLRD and
Protection Against Spurious Writes ................... 81
Unexpected Termination ................................... 81
Write Verify ........................................................ 81
TBLWT (table) ........................................... 76
DS39689A-page 381
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