PIC18F65J90-I/PT Microchip Technology, PIC18F65J90-I/PT Datasheet - Page 248

• Manufacturer Part Number: PIC18F65J90-I/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J90-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 51
• Ram Memory Size: 2KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183030
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F85J90 FAMILY
FIGURE 18-7:
TABLE 18-6:
DS39770C-page 248
INTCON
PIR1
PIE1
IPR1
RCSTA1
RCREG1
TXSTA1
BAUDCON1
SPBRGH1
SPBRG1
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Name
Note:
RX1 (pin)
Rcv Shift Reg
Rcv Buffer Reg
RCREG1
Read Rcv
Buffer Reg
RC1IF
(Interrupt Flag)
OERR bit
CREN bit
This timing diagram shows three words appearing on the RX1 input. The RCREG1 (Receive Buffer register) is read after the third word
causing the OERR (Overrun) bit to be set.
EUSART Receive Register
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
GIE/GIEH PEIE/GIEL TMR0IE
ABDOVF
SPEN
CSRC
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 7
—
—
—
ASYNCHRONOUS RECEPTION
Start
bit
bit 0
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
bit 1
RXDTP
RC1IF
RC1IE
RC1IP
SREN
TXEN
Bit 5
bit 7/8
Stop
TXCKP
INT0IE
CREN
TX1IF
TX1IE
TX1IP
SYNC
bit
Bit 4
Word 1
RCREG1
Start
bit
ADDEN
SENDB
bit 0
BRG16
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
TMR0IF
bit 7/8
BRGH
FERR
Word 2
RCREG1
Bit 2
—
—
—
—
Stop
bit
TMR2IF
TMR2IE
TMR2IP
INT0IF
OERR
TRMT
Start
WUE
 2010 Microchip Technology Inc.
Bit 1
bit
TMR1IF
TMR1IE
TMR1IP
ABDEN
RX9D
TX9D
bit 7/8
RBIF
Bit 0
Stop
bit
on Page
Values
Reset
57
60
60
60
59
59
59
61
61
59