PIC18F65J90-I/PT Microchip Technology, PIC18F65J90-I/PT Datasheet - Page 53
![IC PIC MCU FLASH 16KX16 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F65J90-I/PT
Manufacturer Part Number
PIC18F65J90-I/PT
Description
IC PIC MCU FLASH 16KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F63J11-IPT.pdf
(36 pages)
3.PIC18F63J90-IPT.pdf
(416 pages)
4.PIC18F63J90-IPT.pdf
(22 pages)
5.PIC18F63J90-IPT.pdf
(4 pages)
6.PIC18F63J90-IPT.pdf
(6 pages)
7.PIC18F63J90-IPT.pdf
(6 pages)
8.PIC18F63J90-IPT.pdf
(12 pages)
9.PIC18F85J90-IPT.pdf
(411 pages)
Specifications of PIC18F65J90-I/PT
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
Number Of I /o
51
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Controller Family/series
PIC18
No. Of I/o's
51
Ram Memory Size
2KB
Cpu Speed
40MHz
No. Of Timers
4
No. Of Pwm Channels
2
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
AUSART, EUSART, I2C, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
51
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183030
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Package
64TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F65J90-I/PT
Manufacturer:
VISHAY
Quantity:
2 400
Company:
Part Number:
PIC18F65J90-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F65J90-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC18F63J11-IPT PDF datasheet #2
- PIC18F63J90-IPT PDF datasheet #3
- PIC18F63J90-IPT PDF datasheet #4
- PIC18F63J90-IPT PDF datasheet #5
- PIC18F63J90-IPT PDF datasheet #6
- PIC18F63J90-IPT PDF datasheet #7
- PIC18F63J90-IPT PDF datasheet #8
- PIC18F85J90-IPT PDF datasheet #9
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- Download datasheet (4Mb)
5.2
The MCLR pin provides a method for triggering a hard
external Reset of the device. A Reset is generated by
holding the pin low. PIC18 extended microcontroller
devices have a noise filter in the MCLR Reset path
which detects and ignores small pulses.
The MCLR pin is not driven low by any internal Resets,
including the WDT.
5.3
A Power-on Reset condition is generated on-chip
whenever V
allows the device to start in the initialized state when
V
To take advantage of the POR circuitry, tie the MCLR
pin through a resistor (1 k to 10 k) to V
eliminate external RC components usually needed to
create a Power-on Reset delay. A minimum rise rate for
V
time, see Figure 5-2.
When the device starts normal operation (i.e., exits the
Reset
(voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
Power-on Reset events are captured by the POR bit
(RCON<1>). The state of the bit is set to ‘0’ whenever
a Power-on Reset occurs; it does not change for any
other Reset event. POR is not reset to ‘1’ by any
hardware event. To capture multiple events, the user
manually resets the bit to ‘1’ in software following any
Power-on Reset.
5.4
The PIC18F85J90 family of devices incorporates a
simple BOR function when the internal regulator is
enabled (ENVREG pin is tied to V
ulator will trigger a Brown-out Reset when output of the
regulator to the device core approaches the voltage at
which the device is unable to run at full speed. The
BOR circuit also keeps the device in Reset as V
rises, until the regulator’s output level is sufficient for
full-speed operation.
Once a BOR has occurred, the Power-up Timer will
keep the chip in Reset for T
V
while the Power-up Timer is running, the chip will go
back into a Brown-out Reset and the Power-up Timer
will be initialized. Once V
regulator output is sufficient, the Power-up Timer will
execute the additional time delay.
2010 Microchip Technology Inc.
DD
DD
DD
drops below the threshold for full-speed operation
is adequate for operation.
is specified (parameter D004). For a slow rise
condition),
Master Clear (MCLR)
Power-on Reset (POR)
Brown-out Reset (BOR)
DD
rises above a certain threshold. This
device
DD
rises to the point where
PWRT
operating
DD
). The voltage reg-
(parameter 33). If
DD
parameters
. This will
DD
PIC18F85J90 FAMILY
FIGURE 5-2:
5.4.1
The BOR bit always resets to ‘0’ on any Brown-out
Reset or Power-on Reset event. This makes it difficult
to determine if a Brown-out Reset event has occurred
just by reading the state of BOR alone. A more reliable
method is to simultaneously check the state of both
POR and BOR. This assumes that the POR bit is reset
to ‘1’ in software immediately after any Power-on Reset
event. If BOR is ‘0’ while POR is ‘1’, it can be reliably
assumed that a Brown-out Reset event has occurred.
If the voltage regulator is disabled, Brown-out Reset
functionality is disabled. In this case, the BOR bit
cannot be used to determine a Brown-out Reset event.
The BOR bit is still cleared by a Power-on Reset event.
5.5
The Configuration Mismatch (CM) Reset register is
designed to detect and attempt to recover from
random, memory corrupting events. This includes
Electrostatic Discharge (ESD) events which can cause
widespread, single bit changes throughout the device
and result in catastrophic failure.
In PIC18FXXXX Flash devices, the device Configura-
tion registers (located in the configuration memory
space) are continuously monitored during operation by
comparing their values to complimentary shadow reg-
isters. If a mismatch is detected between the two sets
of registers, a CM Reset automatically occurs.
These events are captured by the CM bit (RCON<5>).
Whenever a CM event occurs, this bit is set to ‘0’. For
any other Reset event, this bit does not change.
Note 1: External Power-on Reset circuit is required
V
2: R < 40 k is recommended to make sure that
3: R1 1 k will limit any current flowing into
Configuration Mismatch (CM)
DD
DETECTING BOR
D
only if the V
The diode D helps discharge the capacitor
quickly when V
the voltage drop across R does not violate
the device’s electrical specification.
MCLR from external capacitor C, in the event
of MCLR/V
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
V
DD
R
C
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW V
DD
PP
DD
R1
power-up slope is too slow.
pin breakdown, due to
powers down.
DD
PIC18F85J90
MCLR
POWER-UP)
DS39770C-page 53
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