ATMEGA3250P-20AUR Atmel, ATMEGA3250P-20AUR Datasheet - Page 101

• Manufacturer Part Number: ATMEGA3250P-20AUR
• Description: MCU AVR 32K FLASH 20MHZ 100TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA3250P-20AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8023F–AVR–07/09
The edge detector generates one clk
(CSn2:0 = 6) edge it detects.
Figure 14-8. T1/T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the T1/T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least
one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (f
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than f
An external clock source can not be prescaled.
Figure 14-9. Prescaler for Timer/Counter0 and Timer/Counter1
Note:
PSR10
clk
T0
T1
Tn
I/O
1. The synchronization logic on the input pins (
clk
I/O
Synchronization
Synchronization
D
LE
ExtClk
Q
Synchronization
< f
D
clk_I/O
Q
/2) given a 50/50% duty cycle. Since the edge detector uses
T1
clk
/clk
Clear
T1
T
0
pulse for each positive (CSn2:0 = 7) or negative
T1/T0)
ATmega325P/3250P
is shown in
D
Q
(1)
Figure
Edge Detector
14-8.
clk
T0
clk_I/O
Tn_sync
(To Clock
Select Logic)
/2.5.
101