ATMEGA3250P-20AUR Atmel, ATMEGA3250P-20AUR Datasheet - Page 49

• Manufacturer Part Number: ATMEGA3250P-20AUR
• Description: MCU AVR 32K FLASH 20MHZ 100TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA3250P-20AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.4
10.4.1
10.4.2
8023F–AVR–07/09
Watchdog Timer
Timed Sequences for Changing the Configuration of the Watchdog Timer
Safety Level 1
ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three
conditions above to ensure that the reference is turned off before entering Power-down mode.
The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz. This is
the typical value at V
controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as
shown in
dog Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs.
Eight different clock cycle periods can be selected to determine the reset period. If the reset
period expires without another Watchdog Reset, the ATmega325P/3250P resets and executes
from the Reset Vector. For timing details on the Watchdog Reset, refer to
51.
To prevent unintentional disabling of the Watchdog or unintentional change of time-out period,
two different safety levels are selected by the fuse WDTON as shown in
”Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 49
details.
Table 10-1.
Figure 10-7. Watchdog Timer
The sequence for changing configuration differs slightly between the two safety levels. Separate
procedures are described for each level.
In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit
to 1 without any restriction. A timed sequence is needed when changing the Watchdog Time-out
period or disabling an enabled Watchdog Timer. To disable an enabled Watchdog Timer, and/or
changing the Watchdog Time-out, the following procedure must be followed:
WDTON
Unprogrammed
Programmed
Table 10-2 on page
WDT Configuration as a Function of the Fuse Settings of WDTON
CC
Safety
Level
= 5V. See characterization data for typical values at other V
1
2
OSCILLATOR
WATCHDOG
51. The WDR – Watchdog Reset – instruction resets the Watch-
WDT Initial
State
Disabled
Enabled
How to Disable the
WDT
Timed sequence
Always enabled
ATmega325P/3250P
How to Change Time-
out
Timed sequence
Timed sequence
Figure 10-1
Table 10-2 on page
CC
levels. By
Refer to
for
49