PIC18LF1330-I/SO Microchip Technology, PIC18LF1330-I/SO Datasheet - Page 128

• Manufacturer Part Number: PIC18LF1330-I/SO
• Description: IC PIC MCU FLASH 4KX16 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF1330-I/SO

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-SOIC (7.5mm Width)
• Controller Family/series: PIC18
• No. Of I/o's: 16
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 256Byte
• Cpu Speed: 40MHz
• No.: RoHS Compliant
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F1230/1330
14.4.4
This mode is available in Continuous Up/Down Count
mode. In the Double Update mode (PTMOD<1:0> = 11),
an interrupt event is generated each time the PTMR
register is equal to zero and each time the PTMR
matches the PTPER register. Figure 14-8 shows the
interrupts in Continuous Up/Down Count mode with
double updates.
The Double Update mode provides two additional
functions to the user in Center-Aligned mode.
1.
FIGURE 14-8:
DS39758D-page 128
Note 1: Interrupt flag bit, PTIF, is sampled here (every Q1).
PTMR_INT_REQ
PTMR_INT_REQ
A: PRESCALER = 1:1
The control loop bandwidth is doubled because
the PWM duty cycles can be updated twice per
period.
2: PWM Time Base Period register, PTPER, is loaded with the value 3FFh for this example.
PTDIR bit
PTDIR bit
PTIF bit
PTIF bit
PTMR
PTMR
OSC1
OSC1
INTERRUPTS IN DOUBLE UPDATE
MODE
Case 1: PTMR Counting Upwards
Case 2: PTMR Counting Downwards
Q1
Q1
1
1
Q2
Q2
PWM TIME BASE INTERRUPTS, CONTINUOUS UP/DOWN COUNT MODE WITH
DOUBLE UPDATES
3FDh
002h
Q3
Q3
Q4
Q4
Q1
Q1
1
1
Q2
Q2
3FEh
001h
Q3
Q3
Q4
Q4
Q1
Q1
1
1
2
Q2
Q2
2.
000h
3FFh
Note:
Q3
Q3
Asymmetrical center-aligned PWM waveforms
can be generated, which are useful for
minimizing output waveform distortion in certain
motor control applications.
Q4
Q4
Do not change the PTMOD bits while
PTEN is active. It will yield unexpected
results. To change the PWM Timer mode
of operation, first clear the PTEN bit, load
PTMOD bits with required data and then
set PTEN.
Q1
Q1
1
1
Q2
Q2
3FEh
001h
Q3
Q3
 2009 Microchip Technology Inc.
Q4
Q4
Q1
Q1
Q2
Q2
3FDh
002h
Q3
Q3
Q4
Q4